forked from OSchip/llvm-project
parent
bbbfb1cfb8
commit
96f981268f
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@ -315,8 +315,9 @@ def G_EXTRACT : Instruction {
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let hasSideEffects = 0;
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}
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// Combine a sequence of generic vregs into a single larger value (starting at
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// bit 0).
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// Insert a sequence of smaller registers into a larger one at the specified
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// indices (interleaved with the values in the operand list "op0, bit0, op1,
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// bit1, ...")).
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def G_INSERT : Instruction {
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let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins unknown:$src, variable_ops);
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