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[ARM] Fix FixConst for ARMCodeGenPrepare 

Part of FixConsts wrongly assumes either a 8- or 16-bit constant
which can result in the wrong constants being generated during
promotion.

Differential Revision: https://reviews.llvm.org/D52032

llvm-svn: 342140
This commit is contained in:
Sam Parker 2018-09-13 14:48:10 +00:00
parent c96cb25a8b
commit 96f77f142b
2 changed files with 13 additions and 21 deletions
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19
llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp
View File

@ -271,13 +271,6 @@ static bool isSafeOverflow(Instruction *I) {
return true; return true;
} }
// Otherwise, if an instruction is using a negative immediate we will need
// to fix it up during the promotion.
for (auto &Op : I->operands()) {
if (auto *Const = dyn_cast<ConstantInt>(Op))
if (Const->isNegative())
return false;
}
return false; return false;
} }
@ -370,19 +363,9 @@ void IRPromoter::Mutate(Type *OrigTy,
}; };
auto FixConst = [&](ConstantInt *Const, Instruction *I) { auto FixConst = [&](ConstantInt *Const, Instruction *I) {
Constant *NewConst = nullptr; Constant *NewConst = isSafeOverflow(I) && Const->isNegative() ?
if (isSafeOverflow(I)) {
NewConst = (Const->isNegative()) ?
ConstantExpr::getSExt(Const, ExtTy) : ConstantExpr::getSExt(Const, ExtTy) :
ConstantExpr::getZExt(Const, ExtTy); ConstantExpr::getZExt(Const, ExtTy);
} else {
uint64_t NewVal = *Const->getValue().getRawData();
if (Const->getType() == Type::getInt16Ty(Ctx))
NewVal &= 0xFFFF;
else
NewVal &= 0xFF;
NewConst = ConstantInt::get(ExtTy, NewVal);
}
I->replaceUsesOfWith(Const, NewConst); I->replaceUsesOfWith(Const, NewConst);
}; };

11
llvm/test/CodeGen/ARM/arm-cgp-icmps.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple=thumbv8.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP ; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP
; RUN: llc -mtriple=thumbv7em %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP ; RUN: llc -mtriple=thumbv7em %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP
; RUN: llc -mtriple=thumbv8 %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP-IMM ; RUN: llc -mtriple=thumbv8 %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP-IMM
@ -279,3 +279,12 @@ entry:
ret i32 %res ret i32 %res
} }
; CHECK-COMMON-LABEL: icmp_i15
; CHECK-COMMON: movw [[MINUS_ONE:r[0-9]+]], #32767
define i32 @icmp_i15(i15 zeroext %arg0, i15 zeroext %arg1) {
%xor = xor i15 %arg0, -1
%cmp = icmp eq i15 %xor, %arg1
%res = select i1 %cmp, i32 21, i32 42
ret i32 %res
}