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[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions. 

The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior.

llvm-svn: 213850
This commit is contained in:
Tilmann Scheller 2014-07-24 09:55:46 +00:00
parent bdcfab117c
commit 96ef72e54a
2 changed files with 18 additions and 0 deletions
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2
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5732,6 +5732,8 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
case ARM::STR_PRE_REG:
case ARM::STR_POST_IMM:
case ARM::STR_POST_REG:
case ARM::STRH_PRE:
case ARM::STRH_POST:
case ARM::STRB_PRE_IMM:
case ARM::STRB_PRE_REG:
case ARM::STRB_POST_IMM:

16
llvm/test/MC/ARM/diagnostics.s
View File

@ -496,6 +496,10 @@ foo2:
str r0, [r0, r1]!
str r0, [r0], #4
str r0, [r0], r1
strh r0, [r0, #2]!
strh r0, [r0, r1]!
strh r0, [r0], #2
strh r0, [r0], r1
strb r0, [r0, #1]!
strb r0, [r0, r1]!
strb r0, [r0], #1
@ -513,6 +517,18 @@ foo2:
@ CHECK-ERRORS: str r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strh r0, [r0, #2]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strh r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strh r0, [r0], #2
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strh r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0, #1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical