forked from OSchip/llvm-project
gn build: Add AMDGPU target
Differential Revision: https://reviews.llvm.org/D65767 llvm-svn: 367972
This commit is contained in:
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@ -4,7 +4,7 @@ Ideas for things to do:
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- once there are more projects, have an llvm_enable_projects arg, modeled
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after llvm_targets_to_build in the GN build
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- a check-all build target that runs test of all projects
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- more targets (AMDGPU ARC AVR MSP430 XCore)
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- more targets (ARC AVR MSP430 XCore)
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- example: https://reviews.llvm.org/D56416
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- investigate feasibility of working `gn check`
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@ -0,0 +1,24 @@
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import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("AMDGPUGenAsmMatcher") {
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visibility = [ ":AsmParser" ]
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args = [ "-gen-asm-matcher" ]
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td_file = "../AMDGPU.td"
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}
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static_library("AsmParser") {
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output_name = "LLVMAMDGPUAsmParser"
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deps = [
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":AMDGPUGenAsmMatcher",
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"//llvm/lib/MC",
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"//llvm/lib/MC/MCParser",
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"//llvm/lib/Support",
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"//llvm/lib/Target/AMDGPU/MCTargetDesc",
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"//llvm/lib/Target/AMDGPU/TargetInfo",
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"//llvm/lib/Target/AMDGPU/Utils",
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]
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include_dirs = [ ".." ]
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sources = [
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"AMDGPUAsmParser.cpp",
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]
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}
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@ -0,0 +1,197 @@
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import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("AMDGPUGenAsmMatcher") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-asm-matcher" ]
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td_file = "AMDGPU.td"
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}
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tablegen("AMDGPUGenCallingConv") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-callingconv" ]
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td_file = "AMDGPU.td"
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}
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tablegen("AMDGPUGenDAGISel") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-dag-isel" ]
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td_file = "AMDGPU.td"
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}
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tablegen("AMDGPUGenGlobalISel") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-global-isel" ]
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td_file = "AMDGPUGISel.td"
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}
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tablegen("AMDGPUGenMCPseudoLowering") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-pseudo-lowering" ]
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td_file = "AMDGPU.td"
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}
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tablegen("AMDGPUGenRegisterBank") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-register-bank" ]
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td_file = "AMDGPU.td"
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}
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tablegen("R600GenCallingConv") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-callingconv" ]
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td_file = "R600.td"
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}
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tablegen("R600GenDAGISel") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-dag-isel" ]
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td_file = "R600.td"
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}
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tablegen("R600GenDFAPacketizer") {
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visibility = [ ":LLVMAMDGPUCodeGen" ]
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args = [ "-gen-dfa-packetizer" ]
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td_file = "R600.td"
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}
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static_library("LLVMAMDGPUCodeGen") {
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deps = [
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":AMDGPUGenAsmMatcher",
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":AMDGPUGenCallingConv",
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":AMDGPUGenDAGISel",
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":AMDGPUGenGlobalISel",
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":AMDGPUGenMCPseudoLowering",
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":AMDGPUGenRegisterBank",
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":R600GenCallingConv",
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":R600GenDAGISel",
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":R600GenDFAPacketizer",
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"MCTargetDesc",
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"TargetInfo",
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"Utils",
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"//llvm/lib/Analysis",
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"//llvm/lib/CodeGen",
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"//llvm/lib/CodeGen/AsmPrinter",
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"//llvm/lib/CodeGen/GlobalISel",
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"//llvm/lib/CodeGen/MIRParser",
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"//llvm/lib/CodeGen/SelectionDAG",
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"//llvm/lib/IR",
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"//llvm/lib/MC",
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"//llvm/lib/Support",
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"//llvm/lib/Target",
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"//llvm/lib/Transforms/IPO",
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"//llvm/lib/Transforms/Scalar",
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"//llvm/lib/Transforms/Utils",
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]
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include_dirs = [ "." ]
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sources = [
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"AMDGPUAliasAnalysis.cpp",
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"AMDGPUAlwaysInlinePass.cpp",
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"AMDGPUAnnotateKernelFeatures.cpp",
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"AMDGPUAnnotateUniformValues.cpp",
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"AMDGPUArgumentUsageInfo.cpp",
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"AMDGPUAsmPrinter.cpp",
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"AMDGPUAtomicOptimizer.cpp",
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"AMDGPUCallLowering.cpp",
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"AMDGPUCodeGenPrepare.cpp",
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"AMDGPUFixFunctionBitcasts.cpp",
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"AMDGPUFrameLowering.cpp",
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"AMDGPUHSAMetadataStreamer.cpp",
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"AMDGPUISelDAGToDAG.cpp",
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"AMDGPUISelLowering.cpp",
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"AMDGPUInline.cpp",
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"AMDGPUInstrInfo.cpp",
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"AMDGPUInstructionSelector.cpp",
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"AMDGPULegalizerInfo.cpp",
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"AMDGPULibCalls.cpp",
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"AMDGPULibFunc.cpp",
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"AMDGPULowerIntrinsics.cpp",
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"AMDGPULowerKernelArguments.cpp",
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"AMDGPULowerKernelAttributes.cpp",
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"AMDGPUMCInstLower.cpp",
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"AMDGPUMachineCFGStructurizer.cpp",
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"AMDGPUMachineFunction.cpp",
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"AMDGPUMachineModuleInfo.cpp",
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"AMDGPUMacroFusion.cpp",
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"AMDGPUOpenCLEnqueuedBlockLowering.cpp",
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"AMDGPUPerfHintAnalysis.cpp",
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"AMDGPUPromoteAlloca.cpp",
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"AMDGPUPropagateAttributes.cpp",
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"AMDGPURegisterBankInfo.cpp",
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"AMDGPURegisterInfo.cpp",
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"AMDGPURewriteOutArguments.cpp",
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"AMDGPUSubtarget.cpp",
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"AMDGPUTargetMachine.cpp",
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"AMDGPUTargetObjectFile.cpp",
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"AMDGPUTargetTransformInfo.cpp",
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"AMDGPUUnifyDivergentExitNodes.cpp",
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"AMDGPUUnifyMetadata.cpp",
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"AMDILCFGStructurizer.cpp",
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"GCNDPPCombine.cpp",
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"GCNHazardRecognizer.cpp",
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"GCNILPSched.cpp",
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"GCNIterativeScheduler.cpp",
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"GCNMinRegStrategy.cpp",
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"GCNNSAReassign.cpp",
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"GCNRegBankReassign.cpp",
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"GCNRegPressure.cpp",
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"GCNSchedStrategy.cpp",
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"R600AsmPrinter.cpp",
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"R600ClauseMergePass.cpp",
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"R600ControlFlowFinalizer.cpp",
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"R600EmitClauseMarkers.cpp",
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"R600ExpandSpecialInstrs.cpp",
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"R600FrameLowering.cpp",
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"R600ISelLowering.cpp",
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"R600InstrInfo.cpp",
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"R600MachineFunctionInfo.cpp",
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"R600MachineScheduler.cpp",
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"R600OpenCLImageTypeLoweringPass.cpp",
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"R600OptimizeVectorRegisters.cpp",
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"R600Packetizer.cpp",
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"R600RegisterInfo.cpp",
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"SIAddIMGInit.cpp",
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"SIAnnotateControlFlow.cpp",
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"SIFixSGPRCopies.cpp",
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"SIFixVGPRCopies.cpp",
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"SIFixupVectorISel.cpp",
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"SIFoldOperands.cpp",
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"SIFormMemoryClauses.cpp",
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"SIFrameLowering.cpp",
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"SIISelLowering.cpp",
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"SIInsertSkips.cpp",
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"SIInsertWaitcnts.cpp",
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"SIInstrInfo.cpp",
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"SILoadStoreOptimizer.cpp",
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"SILowerControlFlow.cpp",
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"SILowerI1Copies.cpp",
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"SILowerSGPRSpills.cpp",
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"SIMachineFunctionInfo.cpp",
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"SIMachineScheduler.cpp",
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"SIMemoryLegalizer.cpp",
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"SIModeRegister.cpp",
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"SIOptimizeExecMasking.cpp",
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"SIOptimizeExecMaskingPreRA.cpp",
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"SIPeepholeSDWA.cpp",
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"SIPreAllocateWWMRegs.cpp",
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"SIRegisterInfo.cpp",
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"SIShrinkInstructions.cpp",
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"SIWholeQuadMode.cpp",
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]
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}
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# This is a bit different from most build files: Due to this group
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# having the directory's name, "//llvm/lib/Target/AMDGPU" will refer to this
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# target, which pulls in the code in this directory *and all subdirectories*.
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# For most other directories, "//llvm/lib/Foo" only pulls in the code directly
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# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
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# different behavior.
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group("AMDGPU") {
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deps = [
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":LLVMAMDGPUCodeGen",
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"AsmParser",
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"Disassembler",
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"MCTargetDesc",
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"TargetInfo",
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"Utils",
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]
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}
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@ -0,0 +1,24 @@
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import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("AMDGPUGenDisassemblerTables") {
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visibility = [ ":Disassembler" ]
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args = [ "-gen-disassembler" ]
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td_file = "../AMDGPU.td"
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}
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static_library("Disassembler") {
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output_name = "LLVMAMDGPUDisassembler"
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deps = [
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":AMDGPUGenDisassemblerTables",
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"//llvm/lib/MC",
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"//llvm/lib/MC/MCDisassembler",
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"//llvm/lib/Support",
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"//llvm/lib/Target/AMDGPU/MCTargetDesc",
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"//llvm/lib/Target/AMDGPU/TargetInfo",
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"//llvm/lib/Target/AMDGPU/Utils",
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]
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include_dirs = [ ".." ]
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sources = [
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"AMDGPUDisassembler.cpp",
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]
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}
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@ -0,0 +1,112 @@
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import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("AMDGPUGenAsmWriter") {
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visibility = [ ":MCTargetDesc" ]
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args = [ "-gen-asm-writer" ]
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td_file = "../AMDGPU.td"
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}
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tablegen("AMDGPUGenInstrInfo") {
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visibility = [ ":tablegen" ]
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args = [ "-gen-instr-info" ]
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td_file = "../AMDGPU.td"
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}
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tablegen("AMDGPUGenMCCodeEmitter") {
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visibility = [ ":MCTargetDesc" ]
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args = [ "-gen-emitter" ]
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td_file = "../AMDGPU.td"
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}
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tablegen("AMDGPUGenRegisterInfo") {
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visibility = [ ":tablegen" ]
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args = [ "-gen-register-info" ]
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td_file = "../AMDGPU.td"
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}
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tablegen("AMDGPUGenSubtargetInfo") {
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visibility = [ ":tablegen" ]
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args = [ "-gen-subtarget" ]
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td_file = "../AMDGPU.td"
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}
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tablegen("R600GenAsmWriter") {
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visibility = [ ":MCTargetDesc" ]
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args = [ "-gen-asm-writer" ]
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td_file = "../R600.td"
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}
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tablegen("R600GenInstrInfo") {
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visibility = [ ":tablegen" ]
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args = [ "-gen-instr-info" ]
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td_file = "../R600.td"
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}
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tablegen("R600GenMCCodeEmitter") {
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visibility = [ ":MCTargetDesc" ]
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args = [ "-gen-emitter" ]
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td_file = "../R600.td"
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}
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tablegen("R600GenRegisterInfo") {
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visibility = [ ":tablegen" ]
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args = [ "-gen-register-info" ]
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td_file = "../R600.td"
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}
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tablegen("R600GenSubtargetInfo") {
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visibility = [ ":tablegen" ]
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args = [ "-gen-subtarget" ]
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td_file = "../R600.td"
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}
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# This should contain tablegen targets generating .inc files included
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# by other targets. .inc files only used by .cpp files in this directory
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# should be in deps on the static_library instead.
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group("tablegen") {
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visibility = [
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":MCTargetDesc",
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"../Utils",
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]
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public_deps = [
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":AMDGPUGenInstrInfo",
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":AMDGPUGenRegisterInfo",
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":AMDGPUGenSubtargetInfo",
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":R600GenInstrInfo",
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":R600GenRegisterInfo",
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":R600GenSubtargetInfo",
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]
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}
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static_library("MCTargetDesc") {
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output_name = "LLVMAMDGPUDesc"
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public_deps = [
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":tablegen",
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]
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deps = [
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":AMDGPUGenAsmWriter",
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":AMDGPUGenMCCodeEmitter",
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":R600GenAsmWriter",
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":R600GenMCCodeEmitter",
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"//llvm/lib/BinaryFormat",
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"//llvm/lib/IR",
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"//llvm/lib/MC",
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"//llvm/lib/Support",
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"//llvm/lib/Target/AMDGPU/TargetInfo",
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"//llvm/lib/Target/AMDGPU/Utils",
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]
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include_dirs = [ ".." ]
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sources = [
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"AMDGPUAsmBackend.cpp",
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"AMDGPUELFObjectWriter.cpp",
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"AMDGPUELFStreamer.cpp",
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"AMDGPUInstPrinter.cpp",
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"AMDGPUMCAsmInfo.cpp",
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"AMDGPUMCCodeEmitter.cpp",
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"AMDGPUMCTargetDesc.cpp",
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"AMDGPUTargetStreamer.cpp",
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"R600MCCodeEmitter.cpp",
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"R600MCTargetDesc.cpp",
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"SIMCCodeEmitter.cpp",
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]
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}
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@ -0,0 +1,10 @@
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static_library("TargetInfo") {
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output_name = "LLVMAMDGPUInfo"
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deps = [
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"//llvm/lib/Support",
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]
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include_dirs = [ ".." ]
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sources = [
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"AMDGPUTargetInfo.cpp",
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]
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}
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@ -0,0 +1,33 @@
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import("//llvm/utils/TableGen/tablegen.gni")
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tablegen("AMDGPUGenSearchableTables") {
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visibility = [ ":Utils" ]
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args = [ "-gen-searchable-tables" ]
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td_file = "../AMDGPU.td"
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}
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static_library("Utils") {
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output_name = "LLVMAMDGPUUtils"
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public_deps = [
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":AMDGPUGenSearchableTables",
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]
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deps = [
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"//llvm/lib/BinaryFormat",
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"//llvm/lib/IR",
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"//llvm/lib/MC",
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"//llvm/lib/Support",
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# MCTargetDesc depends on Utils, so we can't depend on the full
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# MCTargetDesc target here: it would form a cycle.
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"//llvm/lib/Target/AMDGPU/MCTargetDesc:tablegen",
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]
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# AMDGPUBaseInfo.h includes a header from MCTargetDesc :-/
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include_dirs = [ ".." ]
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sources = [
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"AMDGPUAsmUtils.cpp",
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"AMDGPUBaseInfo.cpp",
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"AMDGPUPALMetadata.cpp",
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"AMDKernelCodeTUtils.cpp",
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]
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}
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@ -21,6 +21,7 @@ if (llvm_targets_to_build == "host") {
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# FIXME: Port the remaining targets.
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llvm_targets_to_build = [
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"AArch64",
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"AMDGPU",
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"ARM",
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"BPF",
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"Hexagon",
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foreach(target, llvm_targets_to_build) {
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if (target == "AArch64") {
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llvm_build_AArch64 = true
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} else if (target == "AMDGPU") {
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# Nothing to do.
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} else if (target == "ARM") {
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llvm_build_ARM = true
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} else if (target == "BPF") {
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