diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 40a7936cfe28..a57102c6e146 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -927,6 +927,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::STC2L_OPTION:
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       break;
     default:
       Inst.addOperand(MCOperand::CreateReg(0));
@@ -946,6 +948,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
   switch (Inst.getOpcode()) {
     case ARM::LDCL_POST:
     case ARM::STCL_POST:
+    case ARM::LDC2L_POST:
+    case ARM::STC2L_POST:
       imm |= U << 8;
     case ARM::LDC_OPTION:
     case ARM::LDCL_OPTION:
diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
index cf258759379a..66bec91c31fe 100644
--- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
@@ -314,3 +314,6 @@
 
 # CHECK: rfedb	#4!
 0x14 0x0 0x32 0xf9
+
+# CHECK: stc2l	p0, cr0, [r2], #-96
+0x18 0x0 0x62 0xfc