forked from OSchip/llvm-project
Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers and TermRegs. When it sees a definition of R it adds all aliases of R to the corresponding set, so that when it needs to test for membership it only needs to test a single register, rather than worrying about aliases there too. E.g. the final candidate loop just has: unsigned Def = Candidates[i].Def; if (!PhysRegClobbers.test(Def) && ...) { to test whether register Def is multiply defined. However, there was also a shortcut in ProcessMI to make sure we didn't add candidates if we already knew that they would fail the final test. This shortcut was more pessimistic than the final one because it checked whether _any alias_ of the defined register was multiply defined. This is too conservative for targets that define register pairs. E.g. on z, R0 and R1 are sometimes used as a pair, so there is a 128-bit register that aliases both R0 and R1. If a loop used R0 and R1 independently, and the definition of R0 came first, we would be able to hoist the R0 assignment (because that used the final test quoted above) but not the R1 assignment (because that meant we had two definitions of the paired R0/R1 register and would fail the shortcut in ProcessMI). This patch just uses the same check for the ProcessMI shortcut as we use in the final candidate loop. llvm-svn: 188774
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@ -468,12 +468,12 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
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for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) {
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if (PhysRegDefs.test(*AS))
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PhysRegClobbers.set(*AS);
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if (PhysRegClobbers.test(*AS))
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PhysRegDefs.set(*AS);
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}
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if (PhysRegClobbers.test(Reg))
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// MI defined register is seen defined by another instruction in
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// the loop, it cannot be a LICM candidate.
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RuledOut = true;
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PhysRegDefs.set(*AS);
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}
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}
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// Only consider reloads for now and remats which do not have register
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@ -80,3 +80,25 @@ define float @f7(float %in) {
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call void asm sideeffect "blah", "~{f0},~{cc}"()
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ret float %in
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}
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; Test that both registers in a GR128 pair get hoisted.
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define void @f8(i32 %count) {
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; CHECK-LABE: f8
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; CHECK-DAG: lhi %r0, 0
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; CHECK-DAG: lhi %r1, 1
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; CHECK: %loop
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; CHECK-NOT: %r
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; CHECK: blah %r0, %r1
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entry:
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br label %loop
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loop:
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%this = phi i32 [ %count, %entry ], [ %next, %loop ]
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call void asm sideeffect "blah $0, $1", "{r0},{r1}" (i32 0, i32 1)
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%next = sub i32 %this, 1
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%cmp = icmp ne i32 %next, 0
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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