From 9694825d3281e3a7e0e1c0f5774d708f83783af7 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Fri, 7 Oct 2016 19:11:28 +0000 Subject: [PATCH] [Hexagon][NFC] Using documented instruction type name V4LDST instead of MEMOP. llvm-svn: 283582 --- llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td | 4 ++-- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 2 +- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td index e17f71fe4e6a..493d04703da9 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td @@ -17,7 +17,7 @@ // *** Must match BaseInfo.h *** //----------------------------------------------------------------------------// -def TypeMEMOP : IType<9>; +def TypeV4LDST : IType<9>; def TypeNV : IType<10>; def TypeDUPLEX : IType<11>; def TypeCOMPOUND : IType<12>; @@ -132,7 +132,7 @@ class NCJInst pattern = [], let mayLoad = 1, mayStore = 1 in class MEMInst pattern = [], string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0> - : InstHexagon, + : InstHexagon, OpcodeHexagon; class MEMInst_V4 pattern = [], diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index c63f044b7128..759200f3a883 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -41,7 +41,7 @@ namespace HexagonII { TypeST = 6, TypeSYSTEM = 7, TypeXTYPE = 8, - TypeMEMOP = 9, + TypeV4LDST = 9, TypeNV = 10, TypeDUPLEX = 11, TypeCOMPOUND = 12, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 3240e5b7c862..5187798f5889 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -244,7 +244,7 @@ bool HexagonShuffler::check() { if (ISJ->Core.getUnits() == slotSingleStore) ++store0; break; - case HexagonII::TypeMEMOP: + case HexagonII::TypeV4LDST: ++loads; ++stores; ++store1;