forked from OSchip/llvm-project
[SelectionDAG] Fix function name in comment. NFC
llvm-svn: 319009
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@ -243,7 +243,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
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// For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
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// For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
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// are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
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// are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
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// legal and was not scalarized.
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// legal and was not scalarized.
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// See the similar logic in ScalarizeVecRes_VSETCC
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// See the similar logic in ScalarizeVecRes_SETCC
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if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
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if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
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Op = GetScalarizedVector(Op);
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Op = GetScalarizedVector(Op);
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} else {
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} else {
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@ -307,7 +307,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
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SDLoc DL(N);
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SDLoc DL(N);
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// The vselect result and true/value operands needs scalarizing, but it's
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// The vselect result and true/value operands needs scalarizing, but it's
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// not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
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// not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
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// See the similar logic in ScalarizeVecRes_VSETCC
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// See the similar logic in ScalarizeVecRes_SETCC
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if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
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if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
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Cond = GetScalarizedVector(Cond);
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Cond = GetScalarizedVector(Cond);
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} else {
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} else {
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