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Improve handling of #-0 offsets for many more pre-indexed addressing modes. 

llvm-svn: 138754
This commit is contained in:
Owen Anderson 2011-08-29 19:36:44 +00:00
parent d62d51c84d
commit 967674d26c
5 changed files with 30 additions and 13 deletions
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13
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -638,7 +638,8 @@ public:
// Immediate offset in range [-1020, 1020] and a multiple of 4.
if (!Mem.OffsetImm) return true;
int64_t Val = Mem.OffsetImm->getValue();
return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
Val == INT32_MIN;
}
bool isMemRegOffset() const {
if (Kind != Memory || !Mem.OffsetRegNum)
@ -709,7 +710,7 @@ public:
// Immediate offset in range [-4095, 4095].
if (!Mem.OffsetImm) return true;
int64_t Val = Mem.OffsetImm->getValue();
return Val > -4096 && Val < 4096;
return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
}
bool isPostIdxImm8() const {
if (Kind != Immediate)
@ -2565,8 +2566,7 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Parser.Lex(); // Eat the '#'.
E = Parser.getTok().getLoc();
// FIXME: Special case #-0 so we can correctly set the U bit.
bool isNegative = getParser().getTok().is(AsmToken::Minus);
const MCExpr *Offset;
if (getParser().ParseExpression(Offset))
return true;
@ -2578,6 +2578,11 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
if (!CE)
return Error (E, "constant expression expected");
// If the constant was #-0, represent it as INT32_MIN.
int32_t Val = CE->getValue();
if (isNegative && Val == 0)
CE = MCConstantExpr::Create(INT32_MIN, getContext());
// Now we should have the closing ']'
E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::RBrac))

4
llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -446,7 +446,9 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
O << "[" << getRegisterName(MO1.getReg());
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
if (ImmOffs || Op == ARM_AM::sub) {
O << ", #"
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
<< ImmOffs * 4;

4
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -432,8 +432,10 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
bool isAdd = true;
// Special value for #-0
if (SImm == INT32_MIN)
if (SImm == INT32_MIN) {
SImm = 0;
isAdd = false;
}
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (SImm < 0) {

8
llvm/test/MC/ARM/basic-arm-instructions.s
View File

@ -1884,6 +1884,14 @@ Lforward:
@ CHECK: strex r2, r1, [r7] @ encoding: [0x91,0x2f,0x87,0xe1]
@ CHECK: strexd r6, r2, r3, [r8] @ encoding: [0x92,0x6f,0xa8,0xe1]
@------------------------------------------------------------------------------
@ STR
@------------------------------------------------------------------------------
strpl r3, [r10, #-0]!
strpl r3, [r10, #0]!
@ CHECK: strpl r3, [r10, #-0]! @ encoding: [0x00,0x30,0x2a,0x55]
@ CHECK: strpl r3, [r10]! @ encoding: [0x00,0x30,0xaa,0x55]
@------------------------------------------------------------------------------
@ SUB

14
llvm/test/MC/ARM/simple-fp-encoding.s
View File

@ -2,7 +2,7 @@
@ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
vadd.f64 d16, d17, d16
@ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
vadd.f32 s0, s1, s0
@ -47,7 +47,7 @@
@ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee]
vabs.f32 s0, s0
@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
vcvt.f32.f64 s0, d16
@ -116,7 +116,7 @@
@ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ vmrs apsr_nzcv, fpscr
@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
vnegne.f64 d16, d16
@ -173,13 +173,13 @@
@ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
vldr.64 d1, [r2, #32]
vldr.64 d1, [r2, #-32]
@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed]
vldr.64 d2, [r3]
@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
@ CHECK: vldr.64 d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed]
vldr.64 d3, [pc]
vldr.64 d3, [pc,#0]
vldr.64 d3, [pc,#-0]
@ -191,13 +191,13 @@
@ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed]
vldr.32 s1, [r2, #32]
vldr.32 s1, [r2, #-32]
@ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed]
vldr.32 s2, [r3]
@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
@ CHECK: vldr.32 s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed]
vldr.32 s5, [pc]
vldr.32 s5, [pc,#0]
vldr.32 s5, [pc,#-0]