forked from OSchip/llvm-project
AMDGPU: Handle sub of constant for DS offset folding
sub C, x - > add (sub 0, x), C for DS offsets. This is mostly to fix regressions that show up when SeparateConstOffsetFromGEP is enabled. llvm-svn: 247054
This commit is contained in:
Matt Arsenault
parent
640499b1fa
commit
966a94f861
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@ -893,15 +893,39 @@ bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
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Offset = N1;
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return true;
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}
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}
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} else if (Addr.getOpcode() == ISD::SUB) {
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// sub C, x -> add (sub 0, x), C
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if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
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int64_t ByteOffset = C->getSExtValue();
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if (isUInt<16>(ByteOffset)) {
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SDLoc DL(Addr);
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SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
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SDLoc DL(Addr);
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// XXX - This is kind of hacky. Create a dummy sub node so we can check
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// the known bits in isDSOffsetLegal. We need to emit the selected node
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// here, so this is thrown away.
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SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
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Zero, Addr.getOperand(1));
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if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
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MachineSDNode *MachineSub
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= CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
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Zero, Addr.getOperand(1));
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Base = SDValue(MachineSub, 0);
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Offset = Addr.getOperand(0);
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return true;
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}
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}
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}
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} else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
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// If we have a constant address, prefer to put the constant into the
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// offset. This can save moves to load the constant address since multiple
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// operations can share the zero base address register, and enables merging
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// into read2 / write2 instructions.
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SDLoc DL(Addr);
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// If we have a constant address, prefer to put the constant into the
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// offset. This can save moves to load the constant address since multiple
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// operations can share the zero base address register, and enables merging
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// into read2 / write2 instructions.
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if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
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if (isUInt<16>(CAddr->getZExtValue())) {
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SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
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MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
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@ -914,10 +938,11 @@ bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
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// default case
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
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return true;
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}
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// TODO: If offset is too big, put low 16-bit into offset.
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bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
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SDValue &Offset0,
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SDValue &Offset1) const {
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@ -936,9 +961,35 @@ bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
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Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
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return true;
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}
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}
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} else if (Addr.getOpcode() == ISD::SUB) {
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// sub C, x -> add (sub 0, x), C
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if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
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unsigned DWordOffset0 = C->getZExtValue() / 4;
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unsigned DWordOffset1 = DWordOffset0 + 1;
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if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
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if (isUInt<8>(DWordOffset0)) {
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SDLoc DL(Addr);
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SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
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// XXX - This is kind of hacky. Create a dummy sub node so we can check
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// the known bits in isDSOffsetLegal. We need to emit the selected node
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// here, so this is thrown away.
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SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
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Zero, Addr.getOperand(1));
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if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
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MachineSDNode *MachineSub
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= CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
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Zero, Addr.getOperand(1));
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Base = SDValue(MachineSub, 0);
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Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
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Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
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return true;
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}
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}
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}
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} else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
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unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
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unsigned DWordOffset1 = DWordOffset0 + 1;
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assert(4 * DWordOffset0 == CAddr->getZExtValue());
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@ -0,0 +1,125 @@
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
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declare void @llvm.AMDGPU.barrier.local() #2
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declare i32 @llvm.r600.read.tidig.x() #0
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@lds.obj = addrspace(3) global [256 x i32] undef, align 4
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; GCN-LABEL: {{^}}write_ds_sub0_offset0_global:
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; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0
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; GCN: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]]
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; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b
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; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12
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define void @write_ds_sub0_offset0_global() #0 {
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entry:
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%x.i = call i32 @llvm.r600.read.tidig.x() #1
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%sub1 = sub i32 0, %x.i
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%tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
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%arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
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store i32 123, i32 addrspace(3)* %arrayidx
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535
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define void @add_x_shl_neg_to_sub_max_offset() #1 {
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 65535, %shl
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%ptr = inttoptr i32 %add to i8 addrspace(3)*
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store i8 13, i8 addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset_p1:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN: ds_write_b8 [[NEG]], [[K]]{{$}}
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define void @add_x_shl_neg_to_sub_max_offset_p1() #1 {
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 65536, %shl
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%ptr = inttoptr i32 %add to i8 addrspace(3)*
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store i8 13, i8 addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}}
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; GCN: s_endpgm
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define void @add_x_shl_neg_to_sub_multi_use() #1 {
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add0 = add i32 123, %shl
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%add1 = add i32 456, %shl
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%ptr0 = inttoptr i32 %add0 to i32 addrspace(3)*
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store volatile i32 13, i32 addrspace(3)* %ptr0
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%ptr1 = inttoptr i32 %add1 to i32 addrspace(3)*
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store volatile i32 13, i32 addrspace(3)* %ptr1
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use_same_offset:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
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; GCN: s_endpgm
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define void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 {
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 123, %shl
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%ptr = inttoptr i32 %add to i32 addrspace(3)*
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store volatile i32 13, i32 addrspace(3)* %ptr
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store volatile i32 13, i32 addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255
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define void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 {
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 1019, %shl
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%ptr = inttoptr i32 %add to i64 addrspace(3)*
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store i64 123, i64 addrspace(3)* %ptr, align 4
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
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; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}
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define void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 {
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 1020, %shl
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%ptr = inttoptr i32 %add to i64 addrspace(3)*
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store i64 123, i64 addrspace(3)* %ptr, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind noduplicate convergent }
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