forked from OSchip/llvm-project
Generalize CaseBlock a bit more:
Rename LHSBB/RHSBB to TrueBB/FalseBB. Allow the RHS value to be null, in which case the LHS is treated as a bool. llvm-svn: 31166
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llvm
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@ -83,17 +83,17 @@ public:
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/// case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs,
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MachineBasicBlock *lhs, MachineBasicBlock *rhs,
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MachineBasicBlock *me) :
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CC(cc), CmpLHS(cmplhs), CmpRHS(cmprhs), LHSBB(lhs), RHSBB(rhs), ThisBB(me){}
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me)
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: CC(cc), CmpLHS(cmplhs), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS - The LHS/RHS of the comparison to emit.
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// CmpLHS/CmpRHS - The LHS/RHS of the comparison to emit. If CmpRHS is
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// null, CmpLHS is treated as a bool condition for the branch.
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Value *CmpLHS, *CmpRHS;
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// LHSBB - the block to branch to if the setcc is true
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MachineBasicBlock *LHSBB;
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// RHSBB - the block to branch to if the setcc is false
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MachineBasicBlock *RHSBB;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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};
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@ -766,7 +766,6 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
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void SelectionDAGLowering::visitBr(BranchInst &I) {
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// Update machine-CFG edges.
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MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
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CurMBB->addSuccessor(Succ0MBB);
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// Figure out which block is immediately after the current one.
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MachineBasicBlock *NextBlock = 0;
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@ -779,48 +778,67 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
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if (Succ0MBB != NextBlock)
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DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
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DAG.getBasicBlock(Succ0MBB)));
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} else {
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MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
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CurMBB->addSuccessor(Succ1MBB);
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SDOperand Cond = getValue(I.getCondition());
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if (Succ1MBB == NextBlock) {
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// If the condition is false, fall through. This means we should branch
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// if the condition is true to Succ #0.
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DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
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Cond, DAG.getBasicBlock(Succ0MBB)));
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} else if (Succ0MBB == NextBlock) {
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// If the condition is true, fall through. This means we should branch if
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// the condition is false to Succ #1. Invert the condition first.
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// Update machine-CFG edges.
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CurMBB->addSuccessor(Succ0MBB);
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return;
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}
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// If this condition is one of the special cases we handle, do special stuff
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// now.
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Value *CondVal = I.getCondition();
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// Update machine-CFG edges.
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CurMBB->addSuccessor(Succ0MBB);
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MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
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CurMBB->addSuccessor(Succ1MBB);
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SDOperand Cond = getValue(CondVal);
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if (Succ1MBB == NextBlock) {
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// If the condition is false, fall through. This means we should branch
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// if the condition is true to Succ #0.
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DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
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Cond, DAG.getBasicBlock(Succ0MBB)));
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} else if (Succ0MBB == NextBlock) {
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// If the condition is true, fall through. This means we should branch if
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// the condition is false to Succ #1. Invert the condition first.
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SDOperand True = DAG.getConstant(1, Cond.getValueType());
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Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
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DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
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Cond, DAG.getBasicBlock(Succ1MBB)));
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} else {
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std::vector<SDOperand> Ops;
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Ops.push_back(getRoot());
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// If the false case is the current basic block, then this is a self
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// loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
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// adds an extra instruction in the loop. Instead, invert the
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// condition and emit "Loop: ... br!cond Loop; br Out.
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if (CurMBB == Succ1MBB) {
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std::swap(Succ0MBB, Succ1MBB);
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SDOperand True = DAG.getConstant(1, Cond.getValueType());
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Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
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DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
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Cond, DAG.getBasicBlock(Succ1MBB)));
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} else {
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std::vector<SDOperand> Ops;
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Ops.push_back(getRoot());
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// If the false case is the current basic block, then this is a self
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// loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
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// adds an extra instruction in the loop. Instead, invert the
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// condition and emit "Loop: ... br!cond Loop; br Out.
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if (CurMBB == Succ1MBB) {
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std::swap(Succ0MBB, Succ1MBB);
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SDOperand True = DAG.getConstant(1, Cond.getValueType());
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Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
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}
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SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
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DAG.getBasicBlock(Succ0MBB));
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DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
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DAG.getBasicBlock(Succ1MBB)));
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}
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SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
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DAG.getBasicBlock(Succ0MBB));
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DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
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DAG.getBasicBlock(Succ1MBB)));
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}
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}
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/// visitSwitchCase - Emits the necessary code to represent a single node in
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/// the binary search tree resulting from lowering a switch instruction.
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void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
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SDOperand Cond = DAG.getSetCC(MVT::i1, getValue(CB.CmpLHS),
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getValue(CB.CmpRHS), CB.CC);
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SDOperand Cond;
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SDOperand CondLHS = getValue(CB.CmpLHS);
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// If the CaseBlock has both LHS/RHS comparisons, build the setcc now,
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// otherwise, just use the LHS value as a bool comparison value.
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if (CB.CmpRHS)
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Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
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else
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Cond = CondLHS;
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// Set NextBlock to be the MBB immediately after the current one, if any.
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// This is used to avoid emitting unnecessary branches to the next block.
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@ -831,21 +849,21 @@ void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
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// If the lhs block is the next block, invert the condition so that we can
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// fall through to the lhs instead of the rhs block.
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if (CB.LHSBB == NextBlock) {
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std::swap(CB.LHSBB, CB.RHSBB);
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if (CB.TrueBB == NextBlock) {
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std::swap(CB.TrueBB, CB.FalseBB);
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SDOperand True = DAG.getConstant(1, Cond.getValueType());
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Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
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}
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SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
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DAG.getBasicBlock(CB.LHSBB));
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if (CB.RHSBB == NextBlock)
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DAG.getBasicBlock(CB.TrueBB));
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if (CB.FalseBB == NextBlock)
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DAG.setRoot(BrCond);
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else
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DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
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DAG.getBasicBlock(CB.RHSBB)));
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DAG.getBasicBlock(CB.FalseBB)));
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// Update successor info
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CurMBB->addSuccessor(CB.LHSBB);
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CurMBB->addSuccessor(CB.RHSBB);
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CurMBB->addSuccessor(CB.TrueBB);
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CurMBB->addSuccessor(CB.FalseBB);
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}
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void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
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@ -947,7 +965,6 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
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}
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}
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// Create a CaseBlock record representing a conditional branch to
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// the Case's target mbb if the value being switched on SV is equal
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// to C.
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@ -1098,7 +1115,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
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CaseRange LHSR(CR.Range.first, Pivot);
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CaseRange RHSR(Pivot, CR.Range.second);
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Constant *C = Pivot->first;
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MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
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MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
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// We know that we branch to the LHS if the Value being switched on is
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// less than the Pivot value, C. We use this to optimize our binary
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@ -1110,11 +1127,11 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
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LHSR.first->first == CR.GE &&
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cast<ConstantIntegral>(C)->getZExtValue() ==
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(cast<ConstantIntegral>(CR.GE)->getZExtValue() + 1ULL)) {
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LHSBB = LHSR.first->second;
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TrueBB = LHSR.first->second;
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} else {
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LHSBB = new MachineBasicBlock(LLVMBB);
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CurMF->getBasicBlockList().insert(BBI, LHSBB);
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CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
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TrueBB = new MachineBasicBlock(LLVMBB);
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CurMF->getBasicBlockList().insert(BBI, TrueBB);
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CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
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}
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// Similar to the optimization above, if the Value being switched on is
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@ -1124,18 +1141,18 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
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if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
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cast<ConstantIntegral>(RHSR.first->first)->getZExtValue() ==
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(cast<ConstantIntegral>(CR.LT)->getZExtValue() - 1ULL)) {
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RHSBB = RHSR.first->second;
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FalseBB = RHSR.first->second;
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} else {
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RHSBB = new MachineBasicBlock(LLVMBB);
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CurMF->getBasicBlockList().insert(BBI, RHSBB);
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CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
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FalseBB = new MachineBasicBlock(LLVMBB);
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CurMF->getBasicBlockList().insert(BBI, FalseBB);
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CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
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}
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// Create a CaseBlock record representing a conditional branch to
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// the LHS node if the value being switched on SV is less than C.
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// Otherwise, branch to LHS.
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ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
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SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
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SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
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if (CR.CaseBB == CurMBB)
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visitSwitchCase(CB);
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@ -3733,7 +3750,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
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// from the original BB before switch expansion. Note that PHI nodes can
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// occur multiple times in PHINodesToUpdate. We have to be very careful to
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// handle them the right number of times.
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while ((BB = SwitchCases[i].LHSBB)) { // Handle LHS and RHS.
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while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
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for (MachineBasicBlock::iterator Phi = BB->begin();
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Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
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// This value for this PHI node is recorded in PHINodesToUpdate, get it.
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@ -3748,14 +3765,14 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
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}
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// Don't process RHS if same block as LHS.
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if (BB == SwitchCases[i].RHSBB)
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SwitchCases[i].RHSBB = 0;
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if (BB == SwitchCases[i].FalseBB)
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SwitchCases[i].FalseBB = 0;
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// If we haven't handled the RHS, do so now. Otherwise, we're done.
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SwitchCases[i].LHSBB = SwitchCases[i].RHSBB;
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SwitchCases[i].RHSBB = 0;
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SwitchCases[i].TrueBB = SwitchCases[i].TrueBB;
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SwitchCases[i].FalseBB = 0;
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}
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assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0);
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assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
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}
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}
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