diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 510572e6d412..6e53ec2bb46e 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -243,7 +243,7 @@ MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res,
   LLT PtrTy = Res.getLLTTy(*getMRI());
   LLT MaskTy = LLT::scalar(PtrTy.getSizeInBits());
   Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy);
-  buildConstant(MaskReg, maskTrailingOnes<uint64_t>(NumBits));
+  buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
   return buildPtrMask(Res, Op0, MaskReg);
 }
 
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
index a0cc56677118..a8aac0210b18 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
@@ -23,8 +23,8 @@ body: |
     ; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
     ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
     ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD2]], [[C1]](s64)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
-    ; CHECK: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD2]], [[COPY1]](s64)
+    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
+    ; CHECK: [[PTRMASK:%[0-9]+]]:_(p0) = G_PTRMASK [[PTR_ADD2]], [[C2]](s64)
     ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTRMASK]], [[C]](s64)
     ; CHECK: G_STORE [[PTR_ADD3]](p0), [[COPY]](p0) :: (store 8)
     %0:_(p0) = COPY $x0