forked from OSchip/llvm-project
AMDGPU: Overload return type of llvm.amdgcn.buffer.load.format
Summary: Allow the selection of BUFFER_LOAD_FORMAT_x and _XY. Do this now before the frontend patches land in Mesa. Eventually, we may want to automatically reduce the size of loads at the LLVM IR level, which requires such overloads, and in some cases Mesa can generate them directly. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18255 llvm-svn: 263792
This commit is contained in:
Nicolai Haehnle
parent
ad63638f6d
commit
95e8ffd398
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@ -206,7 +206,7 @@ def int_amdgcn_image_atomic_cmpswap : Intrinsic <
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[]>;
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def int_amdgcn_buffer_load_format : Intrinsic <
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[llvm_v4f32_ty],
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[llvm_anyfloat_ty],
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[llvm_v4i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // vindex(VGPR)
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llvm_i32_ty, // offset(SGPR/VGPR/imm)
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@ -2108,45 +2108,52 @@ def : Pat <
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//===----------------------------------------------------------------------===//
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// buffer_load/store_format patterns
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//===----------------------------------------------------------------------===//
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def : Pat<
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(int_amdgcn_buffer_load_format v4i32:$rsrc, 0,
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(MUBUFIntrinsicOffset i32:$soffset,
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i16:$offset),
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imm:$glc, imm:$slc),
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(BUFFER_LOAD_FORMAT_XYZW_OFFSET $rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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def : Pat<
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(int_amdgcn_buffer_load_format v4i32:$rsrc, i32:$vindex,
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(MUBUFIntrinsicOffset i32:$soffset,
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i16:$offset),
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imm:$glc, imm:$slc),
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(BUFFER_LOAD_FORMAT_XYZW_IDXEN $vindex, $rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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multiclass MUBUF_LoadIntrinsicPat<ValueType vt, string opcode> {
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def : Pat<
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(vt (int_amdgcn_buffer_load_format v4i32:$rsrc, 0,
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(MUBUFIntrinsicOffset i32:$soffset,
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i16:$offset),
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imm:$glc, imm:$slc)),
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(!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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def : Pat<
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(int_amdgcn_buffer_load_format v4i32:$rsrc, 0,
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(MUBUFIntrinsicVOffset i32:$soffset,
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i16:$offset,
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i32:$voffset),
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imm:$glc, imm:$slc),
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(BUFFER_LOAD_FORMAT_XYZW_OFFEN $voffset, $rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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def : Pat<
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(vt (int_amdgcn_buffer_load_format v4i32:$rsrc, i32:$vindex,
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(MUBUFIntrinsicOffset i32:$soffset,
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i16:$offset),
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imm:$glc, imm:$slc)),
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(!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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def : Pat<
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(int_amdgcn_buffer_load_format v4i32:$rsrc, i32:$vindex,
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(MUBUFIntrinsicVOffset i32:$soffset,
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i16:$offset,
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i32:$voffset),
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imm:$glc, imm:$slc),
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(BUFFER_LOAD_FORMAT_XYZW_BOTHEN
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(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
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$rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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def : Pat<
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(vt (int_amdgcn_buffer_load_format v4i32:$rsrc, 0,
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(MUBUFIntrinsicVOffset i32:$soffset,
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i16:$offset,
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i32:$voffset),
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imm:$glc, imm:$slc)),
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(!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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def : Pat<
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(vt (int_amdgcn_buffer_load_format v4i32:$rsrc, i32:$vindex,
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(MUBUFIntrinsicVOffset i32:$soffset,
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i16:$offset,
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i32:$voffset),
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imm:$glc, imm:$slc)),
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(!cast<MUBUF>(opcode # _BOTHEN)
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(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
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$rsrc, $soffset, (as_i16imm $offset),
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(as_i1imm $glc), (as_i1imm $slc), 0)
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>;
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}
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defm : MUBUF_LoadIntrinsicPat<f32, "BUFFER_LOAD_FORMAT_X">;
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defm : MUBUF_LoadIntrinsicPat<v2f32, "BUFFER_LOAD_FORMAT_XY">;
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defm : MUBUF_LoadIntrinsicPat<v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
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def : Pat<
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(int_amdgcn_buffer_store_format v4f32:$vdata, v4i32:$rsrc, 0,
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@ -8,9 +8,9 @@
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;CHECK: s_waitcnt
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define {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
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%data_glc = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
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%data_slc = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
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%data_glc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
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%data_slc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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@ -22,7 +22,7 @@ main_body:
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_immoffs(<4 x i32> inreg) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret <4 x float> %data
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}
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@ -35,9 +35,9 @@ main_body:
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) #0 {
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main_body:
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%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 4156, i1 0, i1 0)
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%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 36860, i1 0, i1 0)
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%d.2 = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 36864, i1 0, i1 0)
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%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4156, i1 0, i1 0)
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%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36860, i1 0, i1 0)
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%d.2 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36864, i1 0, i1 0)
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%d.3 = fadd <4 x float> %d.0, %d.1
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%data = fadd <4 x float> %d.2, %d.3
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ret <4 x float> %data
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@ -51,8 +51,8 @@ main_body:
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_immoffs_reuse(<4 x i32> inreg) #0 {
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main_body:
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%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 4160, i1 0, i1 0)
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%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 4176, i1 0, i1 0)
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%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4160, i1 0, i1 0)
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%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4176, i1 0, i1 0)
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%data = fadd <4 x float> %d.0, %d.1
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ret <4 x float> %data
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}
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@ -62,7 +62,7 @@ main_body:
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
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ret <4 x float> %data
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}
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@ -71,7 +71,7 @@ main_body:
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
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ret <4 x float> %data
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}
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@ -81,7 +81,7 @@ main_body:
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define <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) #0 {
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main_body:
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%ofs = add i32 %1, 58
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
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ret <4 x float> %data
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}
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@ -90,7 +90,7 @@ main_body:
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0)
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ret <4 x float> %data
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}
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@ -100,11 +100,31 @@ main_body:
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0)
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ret <4 x float> %data
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}
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declare <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32>, i32, i32, i1, i1) #1
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;CHECK-LABEL: {{^}}buffer_load_x:
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;CHECK: buffer_load_format_x v0, s[0:3], 0
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;CHECK: s_waitcnt
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define float @buffer_load_x(<4 x i32> inreg %rsrc) #0 {
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main_body:
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%data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
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ret float %data
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}
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;CHECK-LABEL: {{^}}buffer_load_xy:
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;CHECK: buffer_load_format_xy v[0:1], s[0:3], 0
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;CHECK: s_waitcnt
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define <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) #0 {
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main_body:
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%data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
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ret <2 x float> %data
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}
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declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1
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declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1
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declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readonly }
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@ -65,13 +65,13 @@ main_body:
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define void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0)
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ret void
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}
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declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #1
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declare <4 x float> @llvm.amdgcn.buffer.load.format(<4 x i32>, i32, i32, i1, i1) #2
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declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind }
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