forked from OSchip/llvm-project
[mlir][ArmSVE] Add masked arithmetic operations
These instructions map to SVE-specific instrinsics that accept a predicate operand to support control flow in vector code. Differential Revision: https://reviews.llvm.org/D100982
This commit is contained in:
Javier Setoain
parent
f16afcd9b5
commit
95861216ac
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@ -95,6 +95,13 @@ def ScalableVectorType : ArmSVE_Type<"ScalableVector"> {
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}];
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}
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//===----------------------------------------------------------------------===//
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// Additional LLVM type constraints
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//===----------------------------------------------------------------------===//
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def LLVMScalableVectorType :
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Type<CPred<"$_self.isa<::mlir::LLVM::LLVMScalableVectorType>()">,
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"LLVM dialect scalable vector type">;
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//===----------------------------------------------------------------------===//
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// ArmSVE op definitions
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//===----------------------------------------------------------------------===//
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@ -158,6 +165,52 @@ class ScalableIOp<string mnemonic, string op_description,
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"$src1 `,` $src2 attr-dict `:` type($src1)";
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}
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class ScalableMaskedFOp<string mnemonic, string op_description,
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list<OpTrait> traits = []> :
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ArmSVE_Op<mnemonic, !listconcat(traits,
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[AllTypesMatch<["src1", "src2", "res"]>,
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TypesMatchWith<
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"mask has i1 element type and same shape as operands",
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"src1", "mask", "getI1SameShape($_self)">])> {
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let summary = "masked " # op_description # " for scalable vectors of floats";
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let description = [{
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The `arm_sve.}] # mnemonic # [{` operation takes one scalable vector mask
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and two scalable vector operands, and perform floating point }] #
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op_description # [{ on active lanes. Inactive lanes will keep the value of
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the first operand.}];
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let arguments = (ins
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ScalableVectorOf<[I1]>:$mask,
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ScalableVectorOf<[AnyFloat]>:$src1,
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ScalableVectorOf<[AnyFloat]>:$src2
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);
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let results = (outs ScalableVectorOf<[AnyFloat]>:$res);
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let assemblyFormat =
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"$mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)";
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}
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class ScalableMaskedIOp<string mnemonic, string op_description,
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list<OpTrait> traits = []> :
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ArmSVE_Op<mnemonic, !listconcat(traits,
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[AllTypesMatch<["src1", "src2", "res"]>,
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TypesMatchWith<
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"mask has i1 element type and same shape as operands",
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"src1", "mask", "getI1SameShape($_self)">])> {
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let summary = "masked " # op_description # " for scalable vectors of integers";
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let description = [{
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The `arm_sve.}] # mnemonic # [{` operation takes one scalable vector mask
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and two scalable vector operands, and perform integer }] #
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op_description # [{ on active lanes. Inactive lanes will keep the value of
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the first operand.}];
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let arguments = (ins
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ScalableVectorOf<[I1]>:$mask,
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ScalableVectorOf<[I8, I16, I32, I64]>:$src1,
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ScalableVectorOf<[I8, I16, I32, I64]>:$src2
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);
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let results = (outs ScalableVectorOf<[I8, I16, I32, I64]>:$res);
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let assemblyFormat =
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"$mask `,` $src1 `,` $src2 attr-dict `:` type($mask) `,` type($res)";
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}
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def SdotOp : ArmSVE_Op<"sdot",
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[NoSideEffect,
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AllTypesMatch<["src1", "src2"]>,
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@ -321,21 +374,94 @@ def ScalableUDivIOp : ScalableIOp<"divi_unsigned", "unsigned division">;
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def ScalableDivFOp : ScalableFOp<"divf", "division">;
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def ScalableMaskedAddIOp : ScalableMaskedIOp<"masked.addi", "addition",
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[Commutative]>;
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def ScalableMaskedAddFOp : ScalableMaskedFOp<"masked.addf", "addition",
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[Commutative]>;
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def ScalableMaskedSubIOp : ScalableMaskedIOp<"masked.subi", "subtraction">;
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def ScalableMaskedSubFOp : ScalableMaskedFOp<"masked.subf", "subtraction">;
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def ScalableMaskedMulIOp : ScalableMaskedIOp<"masked.muli", "multiplication",
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[Commutative]>;
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def ScalableMaskedMulFOp : ScalableMaskedFOp<"masked.mulf", "multiplication",
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[Commutative]>;
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def ScalableMaskedSDivIOp : ScalableMaskedIOp<"masked.divi_signed",
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"signed division">;
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def ScalableMaskedUDivIOp : ScalableMaskedIOp<"masked.divi_unsigned",
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"unsigned division">;
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def ScalableMaskedDivFOp : ScalableMaskedFOp<"masked.divf", "division">;
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def UmmlaIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"ummla">,
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Arguments<(ins LLVM_AnyVector, LLVM_AnyVector, LLVM_AnyVector)>;
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def SmmlaIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"smmla">,
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Arguments<(ins LLVM_AnyVector, LLVM_AnyVector, LLVM_AnyVector)>;
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def SdotIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"sdot">,
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Arguments<(ins LLVM_AnyVector, LLVM_AnyVector, LLVM_AnyVector)>;
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def UdotIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"udot">,
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Arguments<(ins LLVM_AnyVector, LLVM_AnyVector, LLVM_AnyVector)>;
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedAddIIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"add">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedAddFIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"fadd">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedMulIIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"mul">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedMulFIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"fmul">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedSubIIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"sub">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedSubFIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"fsub">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedSDivIIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"sdiv">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedUDivIIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"udiv">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def ScalableMaskedDivFIntrOp :
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ArmSVE_IntrBinaryOverloadedOp<"fdiv">,
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Arguments<(ins LLVMScalableVectorType, LLVMScalableVectorType,
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LLVMScalableVectorType)>;
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def VectorScaleIntrOp:
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ArmSVE_NonSVEIntrUnaryOverloadedOp<"vscale">;
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@ -21,6 +21,8 @@
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using namespace mlir;
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static Type getI1SameShape(Type type);
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#define GET_OP_CLASSES
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#include "mlir/Dialect/ArmSVE/ArmSVE.cpp.inc"
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@ -59,3 +61,16 @@ void arm_sve::ArmSVEDialect::printType(Type type, DialectAsmPrinter &os) const {
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if (failed(generatedTypePrinter(type, os)))
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llvm_unreachable("unexpected 'arm_sve' type kind");
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}
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//===----------------------------------------------------------------------===//
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// ScalableVector versions of general helpers for comparison ops
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//===----------------------------------------------------------------------===//
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// Return the scalable vector of the same shape and containing i1.
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static Type getI1SameShape(Type type) {
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auto i1Type = IntegerType::get(type.getContext(), 1);
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if (auto sVectorType = type.dyn_cast<arm_sve::ScalableVectorType>())
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return arm_sve::ScalableVectorType::get(type.getContext(),
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sVectorType.getShape(), i1Type);
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return nullptr;
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}
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@ -83,6 +83,33 @@ using UdotOpLowering = OneToOneConvertToLLVMPattern<UdotOp, UdotIntrOp>;
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using UmmlaOpLowering = OneToOneConvertToLLVMPattern<UmmlaOp, UmmlaIntrOp>;
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using VectorScaleOpLowering =
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OneToOneConvertToLLVMPattern<VectorScaleOp, VectorScaleIntrOp>;
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using ScalableMaskedAddIOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedAddIOp,
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ScalableMaskedAddIIntrOp>;
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using ScalableMaskedAddFOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedAddFOp,
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ScalableMaskedAddFIntrOp>;
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using ScalableMaskedSubIOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedSubIOp,
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ScalableMaskedSubIIntrOp>;
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using ScalableMaskedSubFOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedSubFOp,
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ScalableMaskedSubFIntrOp>;
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using ScalableMaskedMulIOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedMulIOp,
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ScalableMaskedMulIIntrOp>;
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using ScalableMaskedMulFOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedMulFOp,
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ScalableMaskedMulFIntrOp>;
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using ScalableMaskedSDivIOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedSDivIOp,
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ScalableMaskedSDivIIntrOp>;
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using ScalableMaskedUDivIOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedUDivIOp,
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ScalableMaskedUDivIIntrOp>;
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using ScalableMaskedDivFOpLowering =
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OneToOneConvertToLLVMPattern<ScalableMaskedDivFOp,
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ScalableMaskedDivFIntrOp>;
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static void
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populateBasicSVEArithmeticExportPatterns(LLVMTypeConverter &converter,
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@ -136,16 +163,52 @@ void mlir::populateArmSVELegalizeForLLVMExportPatterns(
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SmmlaOpLowering,
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UdotOpLowering,
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UmmlaOpLowering,
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VectorScaleOpLowering>(converter);
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VectorScaleOpLowering,
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ScalableMaskedAddIOpLowering,
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ScalableMaskedAddFOpLowering,
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ScalableMaskedSubIOpLowering,
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ScalableMaskedSubFOpLowering,
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ScalableMaskedMulIOpLowering,
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ScalableMaskedMulFOpLowering,
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ScalableMaskedSDivIOpLowering,
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ScalableMaskedUDivIOpLowering,
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ScalableMaskedDivFOpLowering>(converter);
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// clang-format on
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populateBasicSVEArithmeticExportPatterns(converter, patterns);
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}
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void mlir::configureArmSVELegalizeForExportTarget(
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LLVMConversionTarget &target) {
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target.addLegalOp<SdotIntrOp, SmmlaIntrOp, UdotIntrOp, UmmlaIntrOp,
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VectorScaleIntrOp>();
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target.addIllegalOp<SdotOp, SmmlaOp, UdotOp, UmmlaOp, VectorScaleOp>();
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// clang-format off
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target.addLegalOp<SdotIntrOp,
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SmmlaIntrOp,
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UdotIntrOp,
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UmmlaIntrOp,
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VectorScaleIntrOp,
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ScalableMaskedAddIIntrOp,
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ScalableMaskedAddFIntrOp,
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ScalableMaskedSubIIntrOp,
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ScalableMaskedSubFIntrOp,
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ScalableMaskedMulIIntrOp,
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ScalableMaskedMulFIntrOp,
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ScalableMaskedSDivIIntrOp,
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ScalableMaskedUDivIIntrOp,
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ScalableMaskedDivFIntrOp>();
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target.addIllegalOp<SdotOp,
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SmmlaOp,
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UdotOp,
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UmmlaOp,
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VectorScaleOp,
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ScalableMaskedAddIOp,
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ScalableMaskedAddFOp,
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ScalableMaskedSubIOp,
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ScalableMaskedSubFOp,
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ScalableMaskedMulIOp,
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ScalableMaskedMulFOp,
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ScalableMaskedSDivIOp,
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ScalableMaskedUDivIOp,
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ScalableMaskedDivFOp>();
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// clang-format on
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auto hasScalableVectorType = [](TypeRange types) {
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for (Type type : types)
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if (type.isa<arm_sve::ScalableVectorType>())
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@ -55,7 +55,7 @@ func @arm_sve_arithi(%a: !arm_sve.vector<4xi32>,
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%3 = arm_sve.divi_signed %2, %e : !arm_sve.vector<4xi32>
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// CHECK: llvm.udiv {{.*}}: !llvm.vec<? x 4 x i32>
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%4 = arm_sve.divi_unsigned %2, %e : !arm_sve.vector<4xi32>
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return %3 : !arm_sve.vector<4xi32>
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return %4 : !arm_sve.vector<4xi32>
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}
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func @arm_sve_arithf(%a: !arm_sve.vector<4xf32>,
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@ -74,6 +74,53 @@ func @arm_sve_arithf(%a: !arm_sve.vector<4xf32>,
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return %3 : !arm_sve.vector<4xf32>
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}
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func @arm_sve_arithi_masked(%a: !arm_sve.vector<4xi32>,
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%b: !arm_sve.vector<4xi32>,
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%c: !arm_sve.vector<4xi32>,
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%d: !arm_sve.vector<4xi32>,
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%e: !arm_sve.vector<4xi32>,
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%mask: !arm_sve.vector<4xi1>
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) -> !arm_sve.vector<4xi32> {
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// CHECK: arm_sve.intr.add{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x i32>, !llvm.vec<? x 4 x i32>) -> !llvm.vec<? x 4 x i32>
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%0 = arm_sve.masked.addi %mask, %a, %b : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xi32>
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// CHECK: arm_sve.intr.sub{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x i32>, !llvm.vec<? x 4 x i32>) -> !llvm.vec<? x 4 x i32>
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%1 = arm_sve.masked.subi %mask, %0, %c : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xi32>
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// CHECK: arm_sve.intr.mul{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x i32>, !llvm.vec<? x 4 x i32>) -> !llvm.vec<? x 4 x i32>
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%2 = arm_sve.masked.muli %mask, %1, %d : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xi32>
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// CHECK: arm_sve.intr.sdiv{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x i32>, !llvm.vec<? x 4 x i32>) -> !llvm.vec<? x 4 x i32>
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%3 = arm_sve.masked.divi_signed %mask, %2, %e : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xi32>
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// CHECK: arm_sve.intr.udiv{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x i32>, !llvm.vec<? x 4 x i32>) -> !llvm.vec<? x 4 x i32>
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%4 = arm_sve.masked.divi_unsigned %mask, %3, %e : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xi32>
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return %4 : !arm_sve.vector<4xi32>
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}
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func @arm_sve_arithf_masked(%a: !arm_sve.vector<4xf32>,
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%b: !arm_sve.vector<4xf32>,
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%c: !arm_sve.vector<4xf32>,
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%d: !arm_sve.vector<4xf32>,
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%e: !arm_sve.vector<4xf32>,
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%mask: !arm_sve.vector<4xi1>
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) -> !arm_sve.vector<4xf32> {
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// CHECK: arm_sve.intr.fadd{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x f32>, !llvm.vec<? x 4 x f32>) -> !llvm.vec<? x 4 x f32>
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%0 = arm_sve.masked.addf %mask, %a, %b : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xf32>
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// CHECK: arm_sve.intr.fsub{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x f32>, !llvm.vec<? x 4 x f32>) -> !llvm.vec<? x 4 x f32>
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%1 = arm_sve.masked.subf %mask, %0, %c : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xf32>
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// CHECK: arm_sve.intr.fmul{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x f32>, !llvm.vec<? x 4 x f32>) -> !llvm.vec<? x 4 x f32>
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%2 = arm_sve.masked.mulf %mask, %1, %d : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xf32>
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// CHECK: arm_sve.intr.fdiv{{.*}}: (!llvm.vec<? x 4 x i1>, !llvm.vec<? x 4 x f32>, !llvm.vec<? x 4 x f32>) -> !llvm.vec<? x 4 x f32>
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%3 = arm_sve.masked.divf %mask, %2, %e : !arm_sve.vector<4xi1>,
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!arm_sve.vector<4xf32>
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return %3 : !arm_sve.vector<4xf32>
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}
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func @get_vector_scale() -> index {
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// CHECK: arm_sve.vscale
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%0 = arm_sve.vector_scale : index
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@ -56,6 +56,53 @@ func @arm_sve_arithf(%a: !arm_sve.vector<4xf32>,
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return %1 : !arm_sve.vector<4xf32>
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}
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func @arm_sve_masked_arithi(%a: !arm_sve.vector<4xi32>,
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%b: !arm_sve.vector<4xi32>,
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%c: !arm_sve.vector<4xi32>,
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%d: !arm_sve.vector<4xi32>,
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%e: !arm_sve.vector<4xi32>,
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%mask: !arm_sve.vector<4xi1>)
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-> !arm_sve.vector<4xi32> {
|
||||
// CHECK: arm_sve.masked.muli {{.*}}: !arm_sve.vector<4xi1>, !arm_sve.vector
|
||||
%0 = arm_sve.masked.muli %mask, %a, %b : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xi32>
|
||||
// CHECK: arm_sve.masked.addi {{.*}}: !arm_sve.vector<4xi1>, !arm_sve.vector
|
||||
%1 = arm_sve.masked.addi %mask, %0, %c : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xi32>
|
||||
// CHECK: arm_sve.masked.subi {{.*}}: !arm_sve.vector<4xi1>, !arm_sve.vector
|
||||
%2 = arm_sve.masked.subi %mask, %1, %d : !arm_sve.vector<4xi1>,
|
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!arm_sve.vector<4xi32>
|
||||
// CHECK: arm_sve.masked.divi_signed
|
||||
%3 = arm_sve.masked.divi_signed %mask, %2, %e : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xi32>
|
||||
// CHECK: arm_sve.masked.divi_unsigned
|
||||
%4 = arm_sve.masked.divi_unsigned %mask, %3, %e : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xi32>
|
||||
return %2 : !arm_sve.vector<4xi32>
|
||||
}
|
||||
|
||||
func @arm_sve_masked_arithf(%a: !arm_sve.vector<4xf32>,
|
||||
%b: !arm_sve.vector<4xf32>,
|
||||
%c: !arm_sve.vector<4xf32>,
|
||||
%d: !arm_sve.vector<4xf32>,
|
||||
%e: !arm_sve.vector<4xf32>,
|
||||
%mask: !arm_sve.vector<4xi1>)
|
||||
-> !arm_sve.vector<4xf32> {
|
||||
// CHECK: arm_sve.masked.mulf {{.*}}: !arm_sve.vector<4xi1>, !arm_sve.vector
|
||||
%0 = arm_sve.masked.mulf %mask, %a, %b : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xf32>
|
||||
// CHECK: arm_sve.masked.addf {{.*}}: !arm_sve.vector<4xi1>, !arm_sve.vector
|
||||
%1 = arm_sve.masked.addf %mask, %0, %c : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xf32>
|
||||
// CHECK: arm_sve.masked.subf {{.*}}: !arm_sve.vector<4xi1>, !arm_sve.vector
|
||||
%2 = arm_sve.masked.subf %mask, %1, %d : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xf32>
|
||||
// CHECK: arm_sve.masked.divf {{.*}}: !arm_sve.vector<4xi1>, !arm_sve.vector
|
||||
%3 = arm_sve.masked.divf %mask, %2, %e : !arm_sve.vector<4xi1>,
|
||||
!arm_sve.vector<4xf32>
|
||||
return %3 : !arm_sve.vector<4xf32>
|
||||
}
|
||||
|
||||
func @get_vector_scale() -> index {
|
||||
// CHECK: arm_sve.vector_scale : index
|
||||
%0 = arm_sve.vector_scale : index
|
||||
|
|
|
|||
|
|
@ -72,6 +72,73 @@ llvm.func @arm_sve_arithf(%arg0: !llvm.vec<? x 4 x f32>,
|
|||
llvm.return %1 : !llvm.vec<? x 4 x f32>
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_arithi_masked
|
||||
llvm.func @arm_sve_arithi_masked(%arg0: !llvm.vec<? x 4 x i32>,
|
||||
%arg1: !llvm.vec<? x 4 x i32>,
|
||||
%arg2: !llvm.vec<? x 4 x i32>,
|
||||
%arg3: !llvm.vec<? x 4 x i32>,
|
||||
%arg4: !llvm.vec<? x 4 x i32>,
|
||||
%arg5: !llvm.vec<? x 4 x i1>)
|
||||
-> !llvm.vec<? x 4 x i32> {
|
||||
// CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32
|
||||
%0 = "arm_sve.intr.add"(%arg5, %arg0, %arg1) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x i32>,
|
||||
!llvm.vec<? x 4 x i32>)
|
||||
-> !llvm.vec<? x 4 x i32>
|
||||
// CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32
|
||||
%1 = "arm_sve.intr.sub"(%arg5, %0, %arg1) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x i32>,
|
||||
!llvm.vec<? x 4 x i32>)
|
||||
-> !llvm.vec<? x 4 x i32>
|
||||
// CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32
|
||||
%2 = "arm_sve.intr.mul"(%arg5, %1, %arg3) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x i32>,
|
||||
!llvm.vec<? x 4 x i32>)
|
||||
-> !llvm.vec<? x 4 x i32>
|
||||
// CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32
|
||||
%3 = "arm_sve.intr.sdiv"(%arg5, %2, %arg4) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x i32>,
|
||||
!llvm.vec<? x 4 x i32>)
|
||||
-> !llvm.vec<? x 4 x i32>
|
||||
// CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32
|
||||
%4 = "arm_sve.intr.udiv"(%arg5, %3, %arg4) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x i32>,
|
||||
!llvm.vec<? x 4 x i32>)
|
||||
-> !llvm.vec<? x 4 x i32>
|
||||
llvm.return %4 : !llvm.vec<? x 4 x i32>
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <vscale x 4 x float> @arm_sve_arithf_masked
|
||||
llvm.func @arm_sve_arithf_masked(%arg0: !llvm.vec<? x 4 x f32>,
|
||||
%arg1: !llvm.vec<? x 4 x f32>,
|
||||
%arg2: !llvm.vec<? x 4 x f32>,
|
||||
%arg3: !llvm.vec<? x 4 x f32>,
|
||||
%arg4: !llvm.vec<? x 4 x f32>,
|
||||
%arg5: !llvm.vec<? x 4 x i1>)
|
||||
-> !llvm.vec<? x 4 x f32> {
|
||||
// CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32
|
||||
%0 = "arm_sve.intr.fadd"(%arg5, %arg0, %arg1) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x f32>,
|
||||
!llvm.vec<? x 4 x f32>)
|
||||
-> !llvm.vec<? x 4 x f32>
|
||||
// CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32
|
||||
%1 = "arm_sve.intr.fsub"(%arg5, %0, %arg2) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x f32>,
|
||||
!llvm.vec<? x 4 x f32>)
|
||||
-> !llvm.vec<? x 4 x f32>
|
||||
// CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32
|
||||
%2 = "arm_sve.intr.fmul"(%arg5, %1, %arg3) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x f32>,
|
||||
!llvm.vec<? x 4 x f32>)
|
||||
-> !llvm.vec<? x 4 x f32>
|
||||
// CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32
|
||||
%3 = "arm_sve.intr.fdiv"(%arg5, %2, %arg4) : (!llvm.vec<? x 4 x i1>,
|
||||
!llvm.vec<? x 4 x f32>,
|
||||
!llvm.vec<? x 4 x f32>)
|
||||
-> !llvm.vec<? x 4 x f32>
|
||||
llvm.return %3 : !llvm.vec<? x 4 x f32>
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define i64 @get_vector_scale()
|
||||
llvm.func @get_vector_scale() -> i64 {
|
||||
// CHECK: call i64 @llvm.vscale.i64()
|
||||
|
|
|
|||
Loading…
Reference in New Issue