forked from OSchip/llvm-project
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
explicit about which subtarget they refer to, and add AVX versions of the ones we currently don't. Remove old and now wrong comments! llvm-svn: 138515
This commit is contained in:
Bruno Cardoso Lopes
parent
2953d7b320
commit
9566a66a7c
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@ -2986,6 +2986,34 @@ let Predicates = [HasAVX] in {
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// SSE2 with ImmT == Imm8 and XD prefix.
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defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
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VEX;
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let AddedComplexity = 5 in
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def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
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(VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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// Unary v4f32 shuffle with VPSHUF* in order to fold a load.
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def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
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(VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
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(i8 imm:$imm))),
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(VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
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(i8 imm:$imm))),
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(VPSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
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def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
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def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
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(VPSHUFHWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(VPSHUFHWmi addr:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
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(VPSHUFLWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(VPSHUFLWmi addr:$src, imm:$imm)>;
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}
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let Predicates = [HasSSE2] in {
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@ -2997,6 +3025,34 @@ let Predicates = [HasSSE2] in {
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// SSE2 with ImmT == Imm8 and XD prefix.
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defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
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let AddedComplexity = 5 in
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def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
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(PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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// Unary v4f32 shuffle with PSHUF* in order to fold a load.
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def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
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(PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
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(i8 imm:$imm))),
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(PSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
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(i8 imm:$imm))),
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(PSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(PSHUFDri VR128:$src1, imm:$imm)>;
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def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(PSHUFDri VR128:$src1, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
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(PSHUFHWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(PSHUFHWmi addr:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
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(PSHUFLWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
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(i8 imm:$imm))),
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(PSHUFLWmi addr:$src, imm:$imm)>;
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}
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//===---------------------------------------------------------------------===//
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@ -4150,15 +4206,6 @@ def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
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(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
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}
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let AddedComplexity = 5 in
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def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
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(PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
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Requires<[HasSSE2]>;
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// Unary v4f32 shuffle with PSHUF* in order to fold a load.
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def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
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(PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
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Requires<[HasSSE2]>;
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let AddedComplexity = 20 in {
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// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
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def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
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@ -5964,32 +6011,6 @@ def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
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// The AVX version of some but not all of them are described here, and more
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// should come in a near future.
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// Shuffle with PSHUFD instruction folding loads. The first two patterns match
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// SSE2 loads, which are always promoted to v2i64. The last one should match
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// the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
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// in SSE2, how does it ever worked? Anyway, the pattern will remain here until
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// we investigate further.
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
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(i8 imm:$imm))),
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(VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
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(i8 imm:$imm))),
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(PSHUFDmi addr:$src1, imm:$imm)>;
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def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
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(i8 imm:$imm))),
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(PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
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// Shuffle with PSHUFD instruction.
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
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def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(PSHUFDri VR128:$src1, imm:$imm)>;
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def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
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def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
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(PSHUFDri VR128:$src1, imm:$imm)>;
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// Shuffle with MOVHLPS instruction
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def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
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(MOVHLPSrr VR128:$src1, VR128:$src2)>;
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@ -6155,18 +6176,6 @@ def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
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def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
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(MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
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// Shuffle with PSHUFHW
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def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
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(PSHUFHWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
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(PSHUFHWmi addr:$src, imm:$imm)>;
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// Shuffle with PSHUFLW
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def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
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(PSHUFLWri VR128:$src, imm:$imm)>;
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def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
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(PSHUFLWmi addr:$src, imm:$imm)>;
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// Shuffle with MOVLPS
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def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
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(MOVLPSrm VR128:$src1, addr:$src2)>;
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