forked from OSchip/llvm-project
Use pseudo instructions for VST1 and VST2.
llvm-svn: 112357
This commit is contained in:
Bob Wilson
parent
13ee795c42
commit
950882be07
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@ -119,8 +119,9 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI,
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}
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MIB.addReg(D0, getKillRegState(SrcIsKill))
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.addReg(D1, getKillRegState(SrcIsKill))
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.addReg(D2, getKillRegState(SrcIsKill));
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.addReg(D1, getKillRegState(SrcIsKill));
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if (NumRegs > 2)
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MIB.addReg(D2, getKillRegState(SrcIsKill));
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if (NumRegs > 3)
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MIB.addReg(D3, getKillRegState(SrcIsKill));
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MIB = AddDefaultPred(MIB);
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@ -224,6 +225,48 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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MI.eraseFromParent();
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}
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case ARM::VST1q8Pseudo:
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ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break;
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case ARM::VST1q16Pseudo:
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ExpandVST(MBBI, ARM::VST1q16, false, SingleSpc, 2); break;
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case ARM::VST1q32Pseudo:
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ExpandVST(MBBI, ARM::VST1q32, false, SingleSpc, 2); break;
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case ARM::VST1q64Pseudo:
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ExpandVST(MBBI, ARM::VST1q64, false, SingleSpc, 2); break;
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case ARM::VST1q8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q8_UPD, true, SingleSpc, 2); break;
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case ARM::VST1q16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q16_UPD, true, SingleSpc, 2); break;
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case ARM::VST1q32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q32_UPD, true, SingleSpc, 2); break;
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case ARM::VST1q64Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q64_UPD, true, SingleSpc, 2); break;
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case ARM::VST2d8Pseudo:
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ExpandVST(MBBI, ARM::VST2d8, false, SingleSpc, 2); break;
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case ARM::VST2d16Pseudo:
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ExpandVST(MBBI, ARM::VST2d16, false, SingleSpc, 2); break;
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case ARM::VST2d32Pseudo:
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ExpandVST(MBBI, ARM::VST2d32, false, SingleSpc, 2); break;
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case ARM::VST2q8Pseudo:
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ExpandVST(MBBI, ARM::VST2q8, false, SingleSpc, 4); break;
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case ARM::VST2q16Pseudo:
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ExpandVST(MBBI, ARM::VST2q16, false, SingleSpc, 4); break;
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case ARM::VST2q32Pseudo:
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ExpandVST(MBBI, ARM::VST2q32, false, SingleSpc, 4); break;
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case ARM::VST2d8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2d8_UPD, true, SingleSpc, 2); break;
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case ARM::VST2d16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2d16_UPD, true, SingleSpc, 2); break;
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case ARM::VST2d32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2d32_UPD, true, SingleSpc, 2); break;
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case ARM::VST2q8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2q8_UPD, true, SingleSpc, 4); break;
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case ARM::VST2q16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2q16_UPD, true, SingleSpc, 4); break;
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case ARM::VST2q32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2q32_UPD, true, SingleSpc, 4); break;
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case ARM::VST3d8Pseudo:
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ExpandVST(MBBI, ARM::VST3d8, false, SingleSpc, 3); break;
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case ARM::VST3d16Pseudo:
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@ -1256,16 +1256,14 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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SDValue Pred = getAL(CurDAG);
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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SmallVector<SDValue, 10> Ops;
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SmallVector<SDValue, 7> Ops;
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Ops.push_back(MemAddr);
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Ops.push_back(Align);
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// FIXME: This is a temporary flag to distinguish VSTs that have been
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// converted to pseudo instructions.
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bool usePseudoInstrs = (NumVecs >= 3);
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if (is64BitVector) {
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if (NumVecs >= 2) {
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if (NumVecs == 1) {
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Ops.push_back(N->getOperand(3));
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} else {
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SDValue RegSeq;
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SDValue V0 = N->getOperand(0+3);
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SDValue V1 = N->getOperand(1+3);
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@ -1282,124 +1280,61 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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: N->getOperand(3+3);
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RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
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}
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if (usePseudoInstrs)
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Ops.push_back(RegSeq);
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else {
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// Now extract the D registers back out.
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT,
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RegSeq));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT,
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RegSeq));
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if (NumVecs > 2)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,
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RegSeq));
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if (NumVecs > 3)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,
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RegSeq));
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}
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} else {
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Ops.push_back(N->getOperand(3));
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Ops.push_back(RegSeq);
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}
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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unsigned Opc = DOpcodes[OpcodeIndex];
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
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usePseudoInstrs ? 6 : NumVecs+5);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
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}
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EVT RegVT = GetNEONSubregVT(VT);
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if (NumVecs <= 2) {
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// Quad registers are directly supported for VST1 and VST2,
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// storing pairs of D regs.
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// Quad registers are directly supported for VST1 and VST2.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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if (NumVecs == 2) {
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// First extract the pair of Q registers.
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if (NumVecs == 1) {
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Ops.push_back(N->getOperand(3));
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} else {
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// Form a QQ register.
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SDValue Q0 = N->getOperand(3);
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SDValue Q1 = N->getOperand(4);
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// Form a QQ register.
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SDValue QQ = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
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// Now extract the D registers back out.
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
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QQ));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
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QQ));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, RegVT,
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QQ));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, RegVT,
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QQ));
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 5 + 4);
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} else {
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
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N->getOperand(Vec+3)));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
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N->getOperand(Vec+3)));
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}
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
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5 + 2 * NumVecs);
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Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
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}
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
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}
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// Otherwise, quad registers are stored with two separate instructions,
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// where one stores the even registers and the other stores the odd registers.
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// Form the QQQQ REG_SEQUENCE.
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SDValue V[8];
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for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
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V[i] = CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
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N->getOperand(Vec+3));
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V[i+1] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
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N->getOperand(Vec+3));
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}
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if (NumVecs == 3)
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V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, RegVT), 0);
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SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3],
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V[4], V[5], V[6], V[7]), 0);
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SDValue V0 = N->getOperand(0+3);
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SDValue V1 = N->getOperand(1+3);
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SDValue V2 = N->getOperand(2+3);
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SDValue V3 = (NumVecs == 3)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
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: N->getOperand(3+3);
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SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
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// Store the even D registers.
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assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
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Ops.push_back(Reg0); // post-access address offset
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if (usePseudoInstrs)
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Ops.push_back(RegSeq);
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else
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl,
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RegVT, RegSeq));
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Ops.push_back(RegSeq);
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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unsigned Opc = QOpcodes0[OpcodeIndex];
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SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(),
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usePseudoInstrs ? 7 : NumVecs+6);
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MVT::Other, Ops.data(), 7);
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Chain = SDValue(VStA, 1);
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// Store the odd D registers.
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Ops[0] = SDValue(VStA, 0); // MemAddr
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if (usePseudoInstrs)
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Ops[6] = Chain;
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else {
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl,
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RegVT, RegSeq);
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Ops[NumVecs+5] = Chain;
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}
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Ops[6] = Chain;
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Opc = QOpcodes1[OpcodeIndex];
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SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(),
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usePseudoInstrs ? 7 : NumVecs+6);
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MVT::Other, Ops.data(), 7);
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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@ -2267,15 +2202,16 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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case Intrinsic::arm_neon_vst1: {
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unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
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ARM::VST1d32, ARM::VST1d64 };
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unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
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ARM::VST1q32, ARM::VST1q64 };
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unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
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ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
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return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
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}
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case Intrinsic::arm_neon_vst2: {
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unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
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ARM::VST2d32, ARM::VST1q64 };
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unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
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unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
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ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
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unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
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ARM::VST2q32Pseudo };
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return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
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}
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@ -490,6 +490,12 @@ let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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// Classes for VST* pseudo-instructions with multi-register operands.
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// These are expanded to real instructions after register allocation.
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class VSTQPseudo
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: PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, "">;
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class VSTQWBPseudo
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: PseudoNLdSt<(outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
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"$addr.addr = $wb">;
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class VSTQQPseudo
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: PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), IIC_VST, "">;
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class VSTQQWBPseudo
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@ -520,6 +526,11 @@ def VST1q16 : VST1Q<0b0100, "16">;
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def VST1q32 : VST1Q<0b1000, "32">;
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def VST1q64 : VST1Q<0b1100, "64">;
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def VST1q8Pseudo : VSTQPseudo;
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def VST1q16Pseudo : VSTQPseudo;
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def VST1q32Pseudo : VSTQPseudo;
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def VST1q64Pseudo : VSTQPseudo;
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// ...with address register writeback:
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class VST1DWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
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@ -540,6 +551,11 @@ def VST1q16_UPD : VST1QWB<0b0100, "16">;
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def VST1q32_UPD : VST1QWB<0b1000, "32">;
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def VST1q64_UPD : VST1QWB<0b1100, "64">;
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def VST1q8Pseudo_UPD : VSTQWBPseudo;
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def VST1q16Pseudo_UPD : VSTQWBPseudo;
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def VST1q32Pseudo_UPD : VSTQWBPseudo;
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def VST1q64Pseudo_UPD : VSTQWBPseudo;
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// ...with 3 registers (some of these are only for the disassembler):
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class VST1D3<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0110, op7_4, (outs),
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@ -610,6 +626,14 @@ def VST2q8 : VST2Q<0b0000, "8">;
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def VST2q16 : VST2Q<0b0100, "16">;
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def VST2q32 : VST2Q<0b1000, "32">;
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def VST2d8Pseudo : VSTQPseudo;
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def VST2d16Pseudo : VSTQPseudo;
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def VST2d32Pseudo : VSTQPseudo;
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def VST2q8Pseudo : VSTQQPseudo;
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def VST2q16Pseudo : VSTQQPseudo;
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def VST2q32Pseudo : VSTQQPseudo;
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// ...with address register writeback:
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class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
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@ -631,6 +655,14 @@ def VST2q8_UPD : VST2QWB<0b0000, "8">;
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def VST2q16_UPD : VST2QWB<0b0100, "16">;
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def VST2q32_UPD : VST2QWB<0b1000, "32">;
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def VST2d8Pseudo_UPD : VSTQWBPseudo;
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def VST2d16Pseudo_UPD : VSTQWBPseudo;
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def VST2d32Pseudo_UPD : VSTQWBPseudo;
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def VST2q8Pseudo_UPD : VSTQQWBPseudo;
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def VST2q16Pseudo_UPD : VSTQQWBPseudo;
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def VST2q32Pseudo_UPD : VSTQQWBPseudo;
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// ...with double-spaced registers (for disassembly only):
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def VST2b8 : VST2D<0b1001, 0b0000, "8">;
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def VST2b16 : VST2D<0b1001, 0b0100, "16">;
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@ -178,13 +178,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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Stride = 2;
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return true;
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case ARM::VST1q8:
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case ARM::VST1q16:
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case ARM::VST1q32:
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case ARM::VST1q64:
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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case ARM::VST2LNd8:
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case ARM::VST2LNd16:
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case ARM::VST2LNd32:
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@ -192,13 +185,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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NumRegs = 2;
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return true;
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case ARM::VST2q8:
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case ARM::VST2q16:
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case ARM::VST2q32:
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FirstOpnd = 2;
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NumRegs = 4;
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return true;
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case ARM::VST2LNq16:
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case ARM::VST2LNq32:
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FirstOpnd = 2;
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