forked from OSchip/llvm-project
[X86] Remove 128/256-bit masked pmaddubsw and pmaddwd intrinsics. Replace 512-bit masked intrinsic with unmasked intrinsic and a select.
The 128/256-bit versions were no longer used by clang. It uses the legacy SSE/AVX2 version and a select. The 512-bit was changed to the same for consistency. llvm-svn: 329774
This commit is contained in:
Craig Topper
parent
20c8bcae81
commit
9507fa358c
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@ -4793,32 +4793,12 @@ let TargetPrefix = "x86" in {
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def int_x86_avx512_pmulh_w_512 : GCCBuiltin<"__builtin_ia32_pmulhw512">,
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Intrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty,
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llvm_v32i16_ty], [IntrNoMem, Commutative]>;
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def int_x86_avx512_mask_pmaddw_d_128 : // FIXME: remove this intrinsic
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_pmaddw_d_256 : // FIXME: remove this intrinsic
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v16i16_ty, llvm_v16i16_ty, llvm_v8i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_pmaddw_d_512 :
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GCCBuiltin<"__builtin_ia32_pmaddwd512_mask">,
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Intrinsic<[llvm_v16i32_ty],
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[llvm_v32i16_ty, llvm_v32i16_ty, llvm_v16i32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_pmaddubs_w_128 : // FIXME: remove this intrinsic
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v8i16_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_pmaddubs_w_256 : // FIXME: remove this intrinsic
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Intrinsic<[llvm_v16i16_ty],
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[llvm_v32i8_ty, llvm_v32i8_ty, llvm_v16i16_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_pmaddubs_w_512 :
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GCCBuiltin<"__builtin_ia32_pmaddubsw512_mask">,
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Intrinsic<[llvm_v32i16_ty],
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[llvm_v64i8_ty, llvm_v64i8_ty, llvm_v32i16_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_pmaddw_d_512 : GCCBuiltin<"__builtin_ia32_pmaddwd512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v32i16_ty,
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llvm_v32i16_ty], [IntrNoMem, Commutative]>;
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def int_x86_avx512_pmaddubs_w_512 : GCCBuiltin<"__builtin_ia32_pmaddubsw512">,
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Intrinsic<[llvm_v32i16_ty], [llvm_v64i8_ty,
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llvm_v64i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_dbpsadbw_128 :
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GCCBuiltin<"__builtin_ia32_dbpsadbw128_mask">,
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@ -173,6 +173,8 @@ static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
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Name.startswith("avx512.mask.pmul.hr.sw.") || // Added in 7.0
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Name.startswith("avx512.mask.pmulh.w.") || // Added in 7.0
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Name.startswith("avx512.mask.pmulhu.w.") || // Added in 7.0
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Name.startswith("avx512.mask.pmaddw.d.") || // Added in 7.0
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Name.startswith("avx512.mask.pmaddubs.w.") || // Added in 7.0
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Name.startswith("avx512.mask.packsswb.") || // Added in 5.0
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Name.startswith("avx512.mask.packssdw.") || // Added in 5.0
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Name.startswith("avx512.mask.packuswb.") || // Added in 5.0
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@ -1071,6 +1073,24 @@ static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder,
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IID = Intrinsic::x86_avx512_pmulhu_w_512;
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else
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llvm_unreachable("Unexpected intrinsic");
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} else if (Name.startswith("pmaddw.d.")) {
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if (VecWidth == 128)
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IID = Intrinsic::x86_sse2_pmadd_wd;
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else if (VecWidth == 256)
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IID = Intrinsic::x86_avx2_pmadd_wd;
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else if (VecWidth == 512)
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IID = Intrinsic::x86_avx512_pmaddw_d_512;
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else
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llvm_unreachable("Unexpected intrinsic");
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} else if (Name.startswith("pmaddubs.w.")) {
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if (VecWidth == 128)
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IID = Intrinsic::x86_ssse3_pmadd_ub_sw_128;
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else if (VecWidth == 256)
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IID = Intrinsic::x86_avx2_pmadd_ub_sw;
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else if (VecWidth == 512)
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IID = Intrinsic::x86_avx512_pmaddubs_w_512;
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else
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llvm_unreachable("Unexpected intrinsic");
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} else if (Name.startswith("packsswb.")) {
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if (VecWidth == 128)
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IID = Intrinsic::x86_sse2_packsswb_128;
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@ -843,18 +843,6 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::VPERMV, 0),
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X86_INTRINSIC_DATA(avx512_mask_permvar_si_512, VPERM_2OP_MASK,
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X86ISD::VPERMV, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmaddubs_w_128, INTR_TYPE_2OP_MASK,
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X86ISD::VPMADDUBSW, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmaddubs_w_256, INTR_TYPE_2OP_MASK,
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X86ISD::VPMADDUBSW, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmaddubs_w_512, INTR_TYPE_2OP_MASK,
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X86ISD::VPMADDUBSW, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmaddw_d_128, INTR_TYPE_2OP_MASK,
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X86ISD::VPMADDWD, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmaddw_d_256, INTR_TYPE_2OP_MASK,
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X86ISD::VPMADDWD, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmaddw_d_512, INTR_TYPE_2OP_MASK,
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X86ISD::VPMADDWD, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmov_db_128, INTR_TYPE_1OP_MASK,
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X86ISD::VTRUNC, 0),
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X86_INTRINSIC_DATA(avx512_mask_pmov_db_256, INTR_TYPE_1OP_MASK,
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@ -1454,6 +1442,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_packsswb_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
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X86_INTRINSIC_DATA(avx512_packusdw_512, INTR_TYPE_2OP, X86ISD::PACKUS, 0),
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X86_INTRINSIC_DATA(avx512_packuswb_512, INTR_TYPE_2OP, X86ISD::PACKUS, 0),
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X86_INTRINSIC_DATA(avx512_pmaddubs_w_512, INTR_TYPE_2OP,
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X86ISD::VPMADDUBSW, 0),
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X86_INTRINSIC_DATA(avx512_pmaddw_d_512, INTR_TYPE_2OP,
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X86ISD::VPMADDWD, 0),
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X86_INTRINSIC_DATA(avx512_pmul_hr_sw_512, INTR_TYPE_2OP, X86ISD::MULHRS, 0),
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X86_INTRINSIC_DATA(avx512_pmulh_w_512, INTR_TYPE_2OP, ISD::MULHS, 0),
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X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
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@ -2693,3 +2693,51 @@ define <32 x i16>@test_int_x86_avx512_mask_pmulhr_sw_512(<32 x i16> %x0, <32 x i
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%res2 = add <32 x i16> %res, %res1
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ret <32 x i16> %res2
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}
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declare <32 x i16> @llvm.x86.avx512.mask.pmaddubs.w.512(<64 x i8>, <64 x i8>, <32 x i16>, i32)
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define <32 x i16>@test_int_x86_avx512_mask_pmaddubs_w_512(<64 x i8> %x0, <64 x i8> %x1, <32 x i16> %x2, i32 %x3) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_pmaddubs_w_512:
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; AVX512BW: ## %bb.0:
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; AVX512BW-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm3
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; AVX512BW-NEXT: kmovd %edi, %k1
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; AVX512BW-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmaddubs_w_512:
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; AVX512F-32: # %bb.0:
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; AVX512F-32-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm3
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; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
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; AVX512F-32-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <32 x i16> @llvm.x86.avx512.mask.pmaddubs.w.512(<64 x i8> %x0, <64 x i8> %x1, <32 x i16> %x2, i32 %x3)
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%res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaddubs.w.512(<64 x i8> %x0, <64 x i8> %x1, <32 x i16> %x2, i32 -1)
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%res2 = add <32 x i16> %res, %res1
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ret <32 x i16> %res2
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}
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declare <16 x i32> @llvm.x86.avx512.mask.pmaddw.d.512(<32 x i16>, <32 x i16>, <16 x i32>, i16)
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define <16 x i32>@test_int_x86_avx512_mask_pmaddw_d_512(<32 x i16> %x0, <32 x i16> %x1, <16 x i32> %x2, i16 %x3) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_pmaddw_d_512:
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; AVX512BW: ## %bb.0:
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; AVX512BW-NEXT: vpmaddwd %zmm1, %zmm0, %zmm3
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; AVX512BW-NEXT: kmovd %edi, %k1
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; AVX512BW-NEXT: vpmaddwd %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512BW-NEXT: vpaddd %zmm3, %zmm2, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmaddw_d_512:
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; AVX512F-32: # %bb.0:
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; AVX512F-32-NEXT: vpmaddwd %zmm1, %zmm0, %zmm3
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; AVX512F-32-NEXT: kmovw {{[0-9]+}}(%esp), %k1
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; AVX512F-32-NEXT: vpmaddwd %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512F-32-NEXT: vpaddd %zmm3, %zmm2, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <16 x i32> @llvm.x86.avx512.mask.pmaddw.d.512(<32 x i16> %x0, <32 x i16> %x1, <16 x i32> %x2, i16 %x3)
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%res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaddw.d.512(<32 x i16> %x0, <32 x i16> %x1, <16 x i32> %x2, i16 -1)
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%res2 = add <16 x i32> %res, %res1
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ret <16 x i32> %res2
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}
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@ -1361,51 +1361,55 @@ define void @test_int_x86_avx512_mask_pmovus_wb_mem_512(i8* %ptr, <32 x i16> %x1
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ret void
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}
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declare <32 x i16> @llvm.x86.avx512.mask.pmaddubs.w.512(<64 x i8>, <64 x i8>, <32 x i16>, i32)
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declare <32 x i16> @llvm.x86.avx512.pmaddubs.w.512(<64 x i8>, <64 x i8>)
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define <32 x i16>@test_int_x86_avx512_mask_pmaddubs_w_512(<64 x i8> %x0, <64 x i8> %x1, <32 x i16> %x2, i32 %x3) {
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define <32 x i16> @test_int_x86_avx512_mask_pmaddubs_w_512(<64 x i8> %x0, <64 x i8> %x1, <32 x i16> %x2, i32 %x3) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_pmaddubs_w_512:
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; AVX512BW: ## %bb.0:
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; AVX512BW-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm3
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; AVX512BW-NEXT: kmovd %edi, %k1
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; AVX512BW-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512BW-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddw %zmm0, %zmm2, %zmm0
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; AVX512BW-NEXT: vpaddw %zmm3, %zmm2, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmaddubs_w_512:
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; AVX512F-32: # %bb.0:
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; AVX512F-32-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm3
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; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
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; AVX512F-32-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512F-32-NEXT: vpmaddubsw %zmm1, %zmm0, %zmm0
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; AVX512F-32-NEXT: vpaddw %zmm0, %zmm2, %zmm0
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; AVX512F-32-NEXT: vpaddw %zmm3, %zmm2, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <32 x i16> @llvm.x86.avx512.mask.pmaddubs.w.512(<64 x i8> %x0, <64 x i8> %x1, <32 x i16> %x2, i32 %x3)
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%res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaddubs.w.512(<64 x i8> %x0, <64 x i8> %x1, <32 x i16> %x2, i32 -1)
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%res2 = add <32 x i16> %res, %res1
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%1 = call <32 x i16> @llvm.x86.avx512.pmaddubs.w.512(<64 x i8> %x0, <64 x i8> %x1)
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%2 = bitcast i32 %x3 to <32 x i1>
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%3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %x2
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%4 = call <32 x i16> @llvm.x86.avx512.pmaddubs.w.512(<64 x i8> %x0, <64 x i8> %x1)
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%res2 = add <32 x i16> %3, %4
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ret <32 x i16> %res2
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}
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declare <16 x i32> @llvm.x86.avx512.mask.pmaddw.d.512(<32 x i16>, <32 x i16>, <16 x i32>, i16)
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declare <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16>, <32 x i16>)
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define <16 x i32>@test_int_x86_avx512_mask_pmaddw_d_512(<32 x i16> %x0, <32 x i16> %x1, <16 x i32> %x2, i16 %x3) {
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define <16 x i32> @test_int_x86_avx512_mask_pmaddw_d_512(<32 x i16> %x0, <32 x i16> %x1, <16 x i32> %x2, i16 %x3) {
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; AVX512BW-LABEL: test_int_x86_avx512_mask_pmaddw_d_512:
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; AVX512BW: ## %bb.0:
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; AVX512BW-NEXT: vpmaddwd %zmm1, %zmm0, %zmm3
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; AVX512BW-NEXT: kmovd %edi, %k1
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; AVX512BW-NEXT: vpmaddwd %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512BW-NEXT: vpmaddwd %zmm1, %zmm0, %zmm0
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; AVX512BW-NEXT: vpaddd %zmm0, %zmm2, %zmm0
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; AVX512BW-NEXT: vpaddd %zmm3, %zmm2, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512F-32-LABEL: test_int_x86_avx512_mask_pmaddw_d_512:
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; AVX512F-32: # %bb.0:
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; AVX512F-32-NEXT: vpmaddwd %zmm1, %zmm0, %zmm3
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; AVX512F-32-NEXT: kmovw {{[0-9]+}}(%esp), %k1
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; AVX512F-32-NEXT: vpmaddwd %zmm1, %zmm0, %zmm2 {%k1}
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; AVX512F-32-NEXT: vpmaddwd %zmm1, %zmm0, %zmm0
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; AVX512F-32-NEXT: vpaddd %zmm0, %zmm2, %zmm0
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; AVX512F-32-NEXT: vpaddd %zmm3, %zmm2, %zmm0
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; AVX512F-32-NEXT: retl
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%res = call <16 x i32> @llvm.x86.avx512.mask.pmaddw.d.512(<32 x i16> %x0, <32 x i16> %x1, <16 x i32> %x2, i16 %x3)
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%res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaddw.d.512(<32 x i16> %x0, <32 x i16> %x1, <16 x i32> %x2, i16 -1)
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%res2 = add <16 x i32> %res, %res1
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%1 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %x0, <32 x i16> %x1)
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%2 = bitcast i16 %x3 to <16 x i1>
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%3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %x2
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%4 = call <16 x i32> @llvm.x86.avx512.pmaddw.d.512(<32 x i16> %x0, <32 x i16> %x1)
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%res2 = add <16 x i32> %3, %4
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ret <16 x i32> %res2
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}
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@ -3946,3 +3946,67 @@ define <16 x i16>@test_int_x86_avx512_mask_pmulhr_sw_256(<16 x i16> %x0, <16 x i
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%res2 = add <16 x i16> %res, %res1
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ret <16 x i16> %res2
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}
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declare <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8>, <16 x i8>, <8 x i16>, i8)
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define <8 x i16>@test_int_x86_avx512_mask_pmaddubs_w_128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_pmaddubs_w_128:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm3 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x04,0xd9]
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; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
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; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x09,0x04,0xd1]
|
||||
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfd,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3)
|
||||
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 -1)
|
||||
%res2 = add <8 x i16> %res, %res1
|
||||
ret <8 x i16> %res2
|
||||
}
|
||||
|
||||
declare <16 x i16> @llvm.x86.avx512.mask.pmaddubs.w.256(<32 x i8>, <32 x i8>, <16 x i16>, i16)
|
||||
|
||||
define <16 x i16>@test_int_x86_avx512_mask_pmaddubs_w_256(<32 x i8> %x0, <32 x i8> %x1, <16 x i16> %x2, i16 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddubs_w_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm3 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xd9]
|
||||
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
|
||||
; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x04,0xd1]
|
||||
; CHECK-NEXT: vpaddw %ymm3, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfd,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <16 x i16> @llvm.x86.avx512.mask.pmaddubs.w.256(<32 x i8> %x0, <32 x i8> %x1, <16 x i16> %x2, i16 %x3)
|
||||
%res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaddubs.w.256(<32 x i8> %x0, <32 x i8> %x1, <16 x i16> %x2, i16 -1)
|
||||
%res2 = add <16 x i16> %res, %res1
|
||||
ret <16 x i16> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16>, <8 x i16>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_pmaddw_d_128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm3 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf5,0xd9]
|
||||
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
|
||||
; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xf5,0xd1]
|
||||
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfe,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16>, <16 x i16>, <8 x i32>, i8)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_pmaddw_d_256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xd9]
|
||||
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
|
||||
; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xf5,0xd1]
|
||||
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfe,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2212,67 +2212,76 @@ define void @test_int_x86_avx512_mask_pmovus_wb_mem_256(i8* %ptr, <16 x i16> %x1
|
|||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16>, <8 x i16>, <4 x i32>, i8)
|
||||
declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_pmaddw_d_128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3) {
|
||||
define <4 x i32> @test_int_x86_avx512_mask_pmaddw_d_128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm3 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf5,0xd9]
|
||||
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
|
||||
; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xf5,0xd1]
|
||||
; CHECK-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf5,0xc1]
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfe,0xc0]
|
||||
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfe,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 %x3)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaddw.d.128(<8 x i16> %x0, <8 x i16> %x1, <4 x i32> %x2, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
%1 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %x0, <8 x i16> %x1)
|
||||
%2 = bitcast i8 %x3 to <8 x i1>
|
||||
%extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%3 = select <4 x i1> %extract, <4 x i32> %1, <4 x i32> %x2
|
||||
%4 = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %x0, <8 x i16> %x1)
|
||||
%res2 = add <4 x i32> %3, %4
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16>, <16 x i16>, <8 x i32>, i8)
|
||||
declare <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16>, <16 x i16>)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_pmaddw_d_256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3) {
|
||||
define <8 x i32> @test_int_x86_avx512_mask_pmaddw_d_256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddw_d_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xd9]
|
||||
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
|
||||
; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xf5,0xd1]
|
||||
; CHECK-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xc1]
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfe,0xc0]
|
||||
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfe,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 %x3)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaddw.d.256(<16 x i16> %x0, <16 x i16> %x1, <8 x i32> %x2, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
%1 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %x0, <16 x i16> %x1)
|
||||
%2 = bitcast i8 %x3 to <8 x i1>
|
||||
%3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %x2
|
||||
%4 = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %x0, <16 x i16> %x1)
|
||||
%res2 = add <8 x i32> %3, %4
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8>, <16 x i8>, <8 x i16>, i8)
|
||||
declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8>, <16 x i8>)
|
||||
|
||||
define <8 x i16>@test_int_x86_avx512_mask_pmaddubs_w_128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3) {
|
||||
define <8 x i16> @test_int_x86_avx512_mask_pmaddubs_w_128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddubs_w_128:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm3 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x04,0xd9]
|
||||
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
|
||||
; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x09,0x04,0xd1]
|
||||
; CHECK-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x04,0xc1]
|
||||
; CHECK-NEXT: vpaddw %xmm0, %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfd,0xc0]
|
||||
; CHECK-NEXT: vpaddw %xmm3, %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfd,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 %x3)
|
||||
%res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaddubs.w.128(<16 x i8> %x0, <16 x i8> %x1, <8 x i16> %x2, i8 -1)
|
||||
%res2 = add <8 x i16> %res, %res1
|
||||
%1 = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %x0, <16 x i8> %x1)
|
||||
%2 = bitcast i8 %x3 to <8 x i1>
|
||||
%3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %x2
|
||||
%4 = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<16 x i8> %x0, <16 x i8> %x1)
|
||||
%res2 = add <8 x i16> %3, %4
|
||||
ret <8 x i16> %res2
|
||||
}
|
||||
|
||||
declare <16 x i16> @llvm.x86.avx512.mask.pmaddubs.w.256(<32 x i8>, <32 x i8>, <16 x i16>, i16)
|
||||
declare <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8>, <32 x i8>)
|
||||
|
||||
define <16 x i16>@test_int_x86_avx512_mask_pmaddubs_w_256(<32 x i8> %x0, <32 x i8> %x1, <16 x i16> %x2, i16 %x3) {
|
||||
define <16 x i16> @test_int_x86_avx512_mask_pmaddubs_w_256(<32 x i8> %x0, <32 x i8> %x1, <16 x i16> %x2, i16 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_pmaddubs_w_256:
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm3 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xd9]
|
||||
; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf]
|
||||
; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x04,0xd1]
|
||||
; CHECK-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
|
||||
; CHECK-NEXT: vpaddw %ymm0, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfd,0xc0]
|
||||
; CHECK-NEXT: vpaddw %ymm3, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfd,0xc3]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
%res = call <16 x i16> @llvm.x86.avx512.mask.pmaddubs.w.256(<32 x i8> %x0, <32 x i8> %x1, <16 x i16> %x2, i16 %x3)
|
||||
%res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaddubs.w.256(<32 x i8> %x0, <32 x i8> %x1, <16 x i16> %x2, i16 -1)
|
||||
%res2 = add <16 x i16> %res, %res1
|
||||
%1 = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %x0, <32 x i8> %x1)
|
||||
%2 = bitcast i16 %x3 to <16 x i1>
|
||||
%3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %x2
|
||||
%4 = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %x0, <32 x i8> %x1)
|
||||
%res2 = add <16 x i16> %3, %4
|
||||
ret <16 x i16> %res2
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue