maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

The different flavors of ARM have different valid subsets of registers. Check 

that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2

llvm-svn: 142706
This commit is contained in:
Bill Wendling 2011-10-22 00:29:28 +00:00
parent c12a271b55
commit 94e6643fce
1 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -6015,9 +6015,19 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
MachineInstrBuilder MIB(&*II);
for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
if (!TRC->contains(SavedRegs[i])) continue;
if (!DefRegs[SavedRegs[i]])
MIB.addReg(SavedRegs[i], RegState::ImplicitDefine | RegState::Dead);
unsigned Reg = SavedRegs[i];
if (Subtarget->isThumb2() &&
!ARM::tGPRRegisterClass->contains(Reg) &&
!ARM::hGPRRegisterClass->contains(Reg))
continue;
else if (Subtarget->isThumb1Only() &&
!ARM::tGPRRegisterClass->contains(Reg))
continue;
else if (!Subtarget->isThumb() &&
!ARM::GPRRegisterClass->contains(Reg))
continue;
if (!DefRegs[Reg])
MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
}
break;