forked from OSchip/llvm-project
parent
dc826fc068
commit
94e5bc9e83
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@ -1653,12 +1653,10 @@ def MFENCE : I<0xAE, MRM6m, (ops),
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
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// MXCSR register
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def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
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"ldmxcsr $src",
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[(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
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def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
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"stmxcsr $dst",
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[(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
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def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
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"ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
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def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
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"stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
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// Thread synchronization
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def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
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