From 94e5bc9e8339fe5d7b3cf91aaf3deddf5b0cb284 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 1 Nov 2006 06:53:52 +0000 Subject: [PATCH] Fix ldmxcsr JIT encoding. llvm-svn: 31343 --- llvm/lib/Target/X86/X86InstrSSE.td | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 7361c70cdfee..f7b8d6142845 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -1653,12 +1653,10 @@ def MFENCE : I<0xAE, MRM6m, (ops), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>; // MXCSR register -def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src), - "ldmxcsr $src", - [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>; -def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst), - "stmxcsr $dst", - [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>; +def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src), + "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>; +def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst), + "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>; // Thread synchronization def MONITOR : I<0xC8, RawFrm, (ops), "monitor",