forked from OSchip/llvm-project
parent
aa8c904dfc
commit
94de7bc3aa
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@ -809,7 +809,7 @@ def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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[(set GPR:$dst, (load addrmode2:$addr))]>;
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[(set GPR:$dst, (load addrmode2:$addr))]>;
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// Special LDR for loads from non-pc-relative constpools.
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// Special LDR for loads from non-pc-relative constpools.
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let isSimpleLoad = 1, isReMaterializable = 1 in
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let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
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"ldr", " $dst, $addr", []>;
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"ldr", " $dst, $addr", []>;
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@ -831,6 +831,7 @@ def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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"ldr", "sb $dst, $addr",
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"ldr", "sb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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let mayLoad = 1 in {
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// Load doubleword
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// Load doubleword
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def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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"ldr", "d $dst, $addr",
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"ldr", "d $dst, $addr",
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@ -876,6 +877,7 @@ def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
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def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
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def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am3offset:$offset), LdFrm,
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(ins GPR:$base,am3offset:$offset), LdFrm,
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"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
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"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
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}
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// Store
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// Store
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def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
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def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
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@ -939,6 +941,7 @@ def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
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//
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//
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// FIXME: $dst1 should be a def.
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// FIXME: $dst1 should be a def.
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let mayLoad = 1 in
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def LDM : AXI4<0x0, (outs),
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def LDM : AXI4<0x0, (outs),
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(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
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(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
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LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
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LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
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@ -265,7 +265,7 @@ def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
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// Special instruction for restore. It cannot clobber condition register
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// Special instruction for restore. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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// when it's expanded by eliminateCallFramePseudoInstr().
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let isSimpleLoad = 1 in
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let isSimpleLoad = 1, mayLoad = 1 in
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def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
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def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
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"ldr $dst, $addr", []>;
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"ldr $dst, $addr", []>;
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@ -276,7 +276,7 @@ def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
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[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
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[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
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// Special LDR for loads from non-pc-relative constpools.
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// Special LDR for loads from non-pc-relative constpools.
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let isSimpleLoad = 1, isReMaterializable = 1 in
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let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
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def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
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"ldr $dst, $addr", []>;
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"ldr $dst, $addr", []>;
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@ -309,6 +309,7 @@ def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
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// TODO: A7-44: LDMIA - load multiple
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// TODO: A7-44: LDMIA - load multiple
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let mayLoad = 1 in
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def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
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def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
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"pop $dst1", []>;
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"pop $dst1", []>;
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@ -110,6 +110,7 @@ def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
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// Load / store multiple Instructions.
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// Load / store multiple Instructions.
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//
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//
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let mayLoad = 1 in {
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def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
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def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
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variable_ops),
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variable_ops),
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"fldm${addr:submode}d${p} ${addr:base}, $dst1",
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"fldm${addr:submode}d${p} ${addr:base}, $dst1",
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@ -119,6 +120,7 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
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variable_ops),
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variable_ops),
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"fldm${addr:submode}s${p} ${addr:base}, $dst1",
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"fldm${addr:submode}s${p} ${addr:base}, $dst1",
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[]>;
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[]>;
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}
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let mayStore = 1 in {
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let mayStore = 1 in {
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def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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@ -24,7 +24,7 @@ def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
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def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
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def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
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def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
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def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
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def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
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def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
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def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, [SDNPMayLoad]>;
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def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet,
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def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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[SDNPHasChain, SDNPOptInFlag]>;
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@ -120,7 +120,8 @@ def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
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def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
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def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
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[SDNPHasChain, SDNPOptInFlag]>;
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[SDNPHasChain, SDNPOptInFlag]>;
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def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
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def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
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[SDNPHasChain, SDNPMayLoad]>;
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def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
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def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
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[SDNPHasChain, SDNPMayStore]>;
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[SDNPHasChain, SDNPMayStore]>;
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@ -36,13 +36,13 @@ def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
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def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
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def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
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[SDNPHasChain, SDNPOutFlag]>;
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[SDNPHasChain, SDNPOutFlag]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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[SDNPHasChain]>;
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[SDNPHasChain, SDNPMayLoad]>;
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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[SDNPHasChain, SDNPInFlag]>;
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[SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
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def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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[SDNPHasChain]>;
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[SDNPHasChain, SDNPMayLoad]>;
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def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
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def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
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[SDNPHasChain, SDNPOutFlag]>;
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[SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
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def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
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def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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[SDNPHasChain]>;
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def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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@ -86,9 +86,10 @@ def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
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[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
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[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
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def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
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def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
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def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
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def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
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SDNPMayLoad]>;
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def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
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def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
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[SDNPHasChain, SDNPOutFlag]>;
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[SDNPHasChain, SDNPOutFlag]>;
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