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get def use info more correct. 

llvm-svn: 45821
This commit is contained in:
Chris Lattner 2008-01-10 05:12:37 +00:00
parent aa8c904dfc
commit 94de7bc3aa
7 changed files with 19 additions and 11 deletions
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5
llvm/lib/Target/ARM/ARMInstrInfo.td
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@ -809,7 +809,7 @@ def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
[(set GPR:$dst, (load addrmode2:$addr))]>; [(set GPR:$dst, (load addrmode2:$addr))]>;
// Special LDR for loads from non-pc-relative constpools. // Special LDR for loads from non-pc-relative constpools.
let isSimpleLoad = 1, isReMaterializable = 1 in let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr", []>; "ldr", " $dst, $addr", []>;
@ -831,6 +831,7 @@ def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
"ldr", "sb $dst, $addr", "ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
let mayLoad = 1 in {
// Load doubleword // Load doubleword
def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
"ldr", "d $dst, $addr", "ldr", "d $dst, $addr",
@ -876,6 +877,7 @@ def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb), def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm, (ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
}
// Store // Store
def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
@ -939,6 +941,7 @@ def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
// //
// FIXME: $dst1 should be a def. // FIXME: $dst1 should be a def.
let mayLoad = 1 in
def LDM : AXI4<0x0, (outs), def LDM : AXI4<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1", LdFrm, "ldm${p}${addr:submode} $addr, $dst1",

5
llvm/lib/Target/ARM/ARMInstrThumb.td
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@ -265,7 +265,7 @@ def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
// Special instruction for restore. It cannot clobber condition register // Special instruction for restore. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr(). // when it's expanded by eliminateCallFramePseudoInstr().
let isSimpleLoad = 1 in let isSimpleLoad = 1, mayLoad = 1 in
def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr), def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
"ldr $dst, $addr", []>; "ldr $dst, $addr", []>;
@ -276,7 +276,7 @@ def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools. // Special LDR for loads from non-pc-relative constpools.
let isSimpleLoad = 1, isReMaterializable = 1 in let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr), def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr", []>; "ldr $dst, $addr", []>;
@ -309,6 +309,7 @@ def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
// TODO: A7-44: LDMIA - load multiple // TODO: A7-44: LDMIA - load multiple
let mayLoad = 1 in
def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins), def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>; "pop $dst1", []>;

2
llvm/lib/Target/ARM/ARMInstrVFP.td
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@ -110,6 +110,7 @@ def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
// Load / store multiple Instructions. // Load / store multiple Instructions.
// //
let mayLoad = 1 in {
def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
variable_ops), variable_ops),
"fldm${addr:submode}d${p} ${addr:base}, $dst1", "fldm${addr:submode}d${p} ${addr:base}, $dst1",
@ -119,6 +120,7 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
variable_ops), variable_ops),
"fldm${addr:submode}s${p} ${addr:base}, $dst1", "fldm${addr:submode}s${p} ${addr:base}, $dst1",
[]>; []>;
}
let mayStore = 1 in { let mayStore = 1 in {
def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,

2
llvm/lib/Target/Alpha/AlphaInstrInfo.td
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@ -24,7 +24,7 @@ def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>; def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>; def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>; def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>; def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, [SDNPMayLoad]>;
def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet, def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;

3
llvm/lib/Target/PowerPC/PPCInstrInfo.td
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@ -120,7 +120,8 @@ def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>; def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
[SDNPHasChain, SDNPMayLoad]>;
def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
[SDNPHasChain, SDNPMayStore]>; [SDNPHasChain, SDNPMayStore]>;

8
llvm/lib/Target/X86/X86InstrFPStack.td
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@ -36,13 +36,13 @@ def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet, def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
[SDNPHasChain, SDNPOutFlag]>; [SDNPHasChain, SDNPOutFlag]>;
def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
[SDNPHasChain]>; [SDNPHasChain, SDNPMayLoad]>;
def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
[SDNPHasChain, SDNPInFlag]>; [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
[SDNPHasChain]>; [SDNPHasChain, SDNPMayLoad]>;
def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild, def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
[SDNPHasChain, SDNPOutFlag]>; [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
[SDNPHasChain]>; [SDNPHasChain]>;
def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,

5
llvm/lib/Target/X86/X86InstrInfo.td
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@ -86,9 +86,10 @@ def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
[SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
SDNPMayLoad]>;
def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
[SDNPHasChain, SDNPOutFlag]>; [SDNPHasChain, SDNPOutFlag]>;