forked from OSchip/llvm-project
[X86] Disable CLWB in Cannon Lake
Cannon Lake does not support CLWB, therefore it does not include all features listed under SKX. Patch by Gabor Buella Differential Revision: https://reviews.llvm.org/D43459 llvm-svn: 325655
This commit is contained in:
parent
d710adac2d
commit
94a940d2b4
|
@ -175,6 +175,7 @@ bool X86TargetInfo::initFeatureMap(
|
|||
setFeatureEnabledImpl(Features, "avx512bw", true);
|
||||
setFeatureEnabledImpl(Features, "avx512vl", true);
|
||||
setFeatureEnabledImpl(Features, "pku", true);
|
||||
if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
|
||||
setFeatureEnabledImpl(Features, "clwb", true);
|
||||
LLVM_FALLTHROUGH;
|
||||
case CK_SkylakeClient:
|
||||
|
|
|
@ -974,7 +974,7 @@
|
|||
// CHECK_CNL_M32: #define __BMI2__ 1
|
||||
// CHECK_CNL_M32: #define __BMI__ 1
|
||||
// CHECK_CNL_M32: #define __CLFLUSHOPT__ 1
|
||||
// CHECK_CNL_M32: #define __CLWB__ 1
|
||||
// CHECK_CNL_M32-NOT: #define __CLWB__ 1
|
||||
// CHECK_CNL_M32: #define __F16C__ 1
|
||||
// CHECK_CNL_M32: #define __FMA__ 1
|
||||
// CHECK_CNL_M32: #define __LZCNT__ 1
|
||||
|
@ -1022,7 +1022,7 @@
|
|||
// CHECK_CNL_M64: #define __BMI2__ 1
|
||||
// CHECK_CNL_M64: #define __BMI__ 1
|
||||
// CHECK_CNL_M64: #define __CLFLUSHOPT__ 1
|
||||
// CHECK_CNL_M64: #define __CLWB__ 1
|
||||
// CHECK_CNL_M64-NOT: #define __CLWB__ 1
|
||||
// CHECK_CNL_M64: #define __F16C__ 1
|
||||
// CHECK_CNL_M64: #define __FMA__ 1
|
||||
// CHECK_CNL_M64: #define __LZCNT__ 1
|
||||
|
|
Loading…
Reference in New Issue