forked from OSchip/llvm-project
[MIPS GlobalISel] Select bswap
G_BSWAP is generated from llvm.bswap.<type> intrinsics, clang genrates these intrinsics from __builtin_bswap32 and __builtin_bswap64. Add lower and narrowscalar for G_BSWAP. Lower G_BSWAP on MIPS32, select G_BSWAP on MIPS32 revision 2 and later. Differential Revision: https://reviews.llvm.org/D71362
This commit is contained in:
Petar Avramovic
parent
cd2a73a9f0
commit
94a24e7a40
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@ -237,6 +237,7 @@ public:
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LegalizeResult lowerExtract(MachineInstr &MI);
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LegalizeResult lowerInsert(MachineInstr &MI);
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LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
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LegalizeResult lowerBswap(MachineInstr &MI);
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private:
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MachineRegisterInfo &MRI;
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@ -1075,6 +1075,27 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_BSWAP: {
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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Observer.changingInstr(MI);
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SmallVector<Register, 2> SrcRegs, DstRegs;
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unsigned NumParts = SizeOp0 / NarrowSize;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
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for (unsigned i = 0; i < NumParts; ++i) {
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auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
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{SrcRegs[NumParts - 1 - i]});
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DstRegs.push_back(DstPart.getReg(0));
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}
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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Observer.changedInstr(MI);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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@ -2289,6 +2310,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return lowerExtract(MI);
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case G_INSERT:
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return lowerInsert(MI);
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case G_BSWAP:
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return lowerBswap(MI);
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}
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}
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@ -4326,3 +4349,38 @@ LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
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MI.eraseFromParent();
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerBswap(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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const LLT Ty = MRI.getType(Src);
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unsigned SizeInBytes = Ty.getSizeInBytes();
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unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
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// Swap most and least significant byte, set remaining bytes in Res to zero.
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auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
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auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
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auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
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auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
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// Set i-th high/low byte in Res to i-th low/high byte from Src.
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for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
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// AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
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APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
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auto Mask = MIRBuilder.buildConstant(Ty, APMask);
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auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
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// Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
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auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
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auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
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Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
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// High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
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auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
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auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
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Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
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}
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Res.getInstr()->getOperand(0).setReg(Dst);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -185,6 +185,19 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder(G_VASTART)
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.legalFor({p0});
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getActionDefinitionsBuilder(G_BSWAP)
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
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return true;
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return false;
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})
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.lowerIf([=, &ST](const LegalityQuery &Query) {
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if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
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return true;
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return false;
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})
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.maxScalar(0, s32);
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// FP instructions
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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@ -451,6 +451,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case G_LSHR:
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case G_BRINDIRECT:
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case G_VASTART:
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case G_BSWAP:
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OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
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break;
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case G_ADD:
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@ -0,0 +1,30 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
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--- |
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define void @bswap_i32() { entry: ret void }
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...
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---
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name: bswap_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32R2-LABEL: name: bswap_i32
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; MIPS32R2: liveins: $a0
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; MIPS32R2: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32R2: [[WSBH:%[0-9]+]]:gpr32 = WSBH [[COPY]]
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; MIPS32R2: [[ROTR:%[0-9]+]]:gpr32 = ROTR [[WSBH]], 16
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; MIPS32R2: $v0 = COPY [[ROTR]]
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; MIPS32R2: RetRA implicit $v0
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%0:gprb(s32) = COPY $a0
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%1:gprb(s32) = G_BSWAP %0
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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@ -0,0 +1,101 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
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--- |
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define void @bswap_i32() { entry: ret void }
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define void @bswap_i64() { entry: ret void }
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...
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---
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name: bswap_i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: bswap_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: $v0 = COPY [[OR2]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32R2-LABEL: name: bswap_i32
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; MIPS32R2: liveins: $a0
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; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
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; MIPS32R2: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_BSWAP %0
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: bswap_i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: bswap_i64
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
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; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL3]]
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; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
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; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]]
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; MIPS32: $v0 = COPY [[OR2]](s32)
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; MIPS32: $v1 = COPY [[OR5]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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; MIPS32R2-LABEL: name: bswap_i64
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; MIPS32R2: liveins: $a0, $a1
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; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
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; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
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; MIPS32R2: $v1 = COPY [[BSWAP1]](s32)
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; MIPS32R2: RetRA implicit $v0, implicit $v1
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%1:_(s32) = COPY $a0
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%2:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
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%3:_(s64) = G_BSWAP %0
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%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
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$v0 = COPY %4(s32)
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$v1 = COPY %5(s32)
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RetRA implicit $v0, implicit $v1
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...
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@ -0,0 +1,68 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mattr=+mips32r2 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32R2
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declare i32 @llvm.bswap.i32(i32)
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define i32 @bswap_i32(i32 %x) {
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; MIPS32-LABEL: bswap_i32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $4, 24
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; MIPS32-NEXT: srl $2, $4, 24
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; MIPS32-NEXT: or $1, $2, $1
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; MIPS32-NEXT: andi $2, $4, 65280
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; MIPS32-NEXT: sll $2, $2, 8
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; MIPS32-NEXT: or $1, $1, $2
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; MIPS32-NEXT: srl $2, $4, 8
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; MIPS32-NEXT: andi $2, $2, 65280
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; MIPS32-NEXT: or $2, $1, $2
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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;
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; MIPS32R2-LABEL: bswap_i32:
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; MIPS32R2: # %bb.0: # %entry
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; MIPS32R2-NEXT: wsbh $1, $4
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; MIPS32R2-NEXT: rotr $2, $1, 16
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; MIPS32R2-NEXT: jr $ra
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; MIPS32R2-NEXT: nop
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entry:
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%0 = tail call i32 @llvm.bswap.i32(i32 %x)
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ret i32 %0
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}
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declare i64 @llvm.bswap.i64(i64)
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define i64 @bswap_i64(i64 %x) {
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; MIPS32-LABEL: bswap_i64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sll $1, $5, 24
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; MIPS32-NEXT: srl $2, $5, 24
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; MIPS32-NEXT: or $1, $2, $1
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; MIPS32-NEXT: andi $2, $5, 65280
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; MIPS32-NEXT: sll $2, $2, 8
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; MIPS32-NEXT: or $1, $1, $2
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; MIPS32-NEXT: srl $2, $5, 8
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; MIPS32-NEXT: andi $2, $2, 65280
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; MIPS32-NEXT: or $2, $1, $2
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; MIPS32-NEXT: sll $1, $4, 24
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; MIPS32-NEXT: srl $3, $4, 24
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; MIPS32-NEXT: or $1, $3, $1
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; MIPS32-NEXT: andi $3, $4, 65280
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; MIPS32-NEXT: sll $3, $3, 8
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; MIPS32-NEXT: or $1, $1, $3
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; MIPS32-NEXT: srl $3, $4, 8
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; MIPS32-NEXT: andi $3, $3, 65280
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; MIPS32-NEXT: or $3, $1, $3
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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;
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; MIPS32R2-LABEL: bswap_i64:
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; MIPS32R2: # %bb.0: # %entry
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; MIPS32R2-NEXT: wsbh $1, $5
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; MIPS32R2-NEXT: rotr $2, $1, 16
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; MIPS32R2-NEXT: wsbh $1, $4
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; MIPS32R2-NEXT: rotr $3, $1, 16
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; MIPS32R2-NEXT: jr $ra
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; MIPS32R2-NEXT: nop
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %x)
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ret i64 %0
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}
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@ -0,0 +1,28 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=regbankselect -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
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--- |
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define void @bswap_i32() { entry: ret void }
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...
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---
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name: bswap_i32
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32R2-LABEL: name: bswap_i32
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; MIPS32R2: liveins: $a0
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; MIPS32R2: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32R2: [[BSWAP:%[0-9]+]]:gprb(s32) = G_BSWAP [[COPY]]
|
||||
; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
|
||||
; MIPS32R2: RetRA implicit $v0
|
||||
%0:_(s32) = COPY $a0
|
||||
%1:_(s32) = G_BSWAP %0
|
||||
$v0 = COPY %1(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue