forked from OSchip/llvm-project
[DAG] Move simplification of SADDSAT/SSUBSAT/UADDSAT/USUBSAT of vXi1 to getNode()
As discussed on D97276 we should be able to always do this in node creation, we don't need a combine.
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@ -2540,10 +2540,6 @@ SDValue DAGCombiner::visitADDSAT(SDNode *N) {
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if (isNullConstant(N1))
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return N0;
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// fold (add_sat x, y) -> (or x, y) for bool types.
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if (VT.getScalarType() == MVT::i1)
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return DAG.getNode(ISD::OR, DL, VT, N0, N1);
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// If it cannot overflow, transform into an add.
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if (Opcode == ISD::UADDSAT)
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if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
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@ -3581,10 +3577,6 @@ SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
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if (isNullConstant(N1))
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return N0;
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// fold (sub_sat x, y) -> (and x, ~y) for bool types.
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if (VT.getScalarType() == MVT::i1)
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return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getNOT(DL, N1, VT));
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return SDValue();
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}
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@ -5342,6 +5342,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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assert(VT.isInteger() && "This operator does not apply to FP types!");
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assert(N1.getValueType() == N2.getValueType() &&
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N1.getValueType() == VT && "Binary operator types must match!");
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
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// fold (add_sat x, y) -> (or x, y) for bool types.
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if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT)
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return getNode(ISD::OR, DL, VT, N1, N2);
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// fold (sub_sat x, y) -> (and x, ~y) for bool types.
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if (Opcode == ISD::SSUBSAT || Opcode == ISD::USUBSAT)
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return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT));
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}
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break;
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case ISD::SMIN:
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case ISD::UMAX:
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