forked from OSchip/llvm-project
[mips] Added -mfp64 and -mfp32 options.
These options specify 64-bit FP registers and 32-bit FP registers respectively. When using -mfp32, the FPU has 16x double-precision registers overlapping with the 32x single-precision registers (each double-precision register overlaps two single-precision registers). When using -mfp64, the FPU has 32x double-precision registers overlapping with the 32x single-precision registers (each double-precision register overlaps with one single-precision register and has an additional 32-bits). MSA requires -mfp64. llvm-svn: 192899
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@ -1104,6 +1104,10 @@ def mmsa : Flag<["-"], "mmsa">, Group<m_Group>,
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HelpText<"Enable MSA ASE (MIPS only)">;
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def mno_msa : Flag<["-"], "mno-msa">, Group<m_Group>,
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HelpText<"Disable MSA ASE (MIPS only)">;
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def mfp64 : Flag<["-"], "mfp64">, Group<m_Group>,
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HelpText<"Use 64-bit floating point registers (MIPS only)">;
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def mfp32 : Flag<["-"], "mfp32">, Group<m_Group>,
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HelpText<"Use 32-bit floating point registers (MIPS only)">;
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def mnan_EQ : Joined<["-"], "mnan=">, Group<m_Group>;
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def mips32 : Flag<["-"], "mips32">,
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Alias<march_EQ>, AliasArgs<["mips32"]>,
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@ -982,6 +982,8 @@ static void getMIPSTargetFeatures(const Driver &D, const ArgList &Args,
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"dspr2");
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AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
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"msa");
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AddTargetFeature(Args, Features, options::OPT_mfp64, options::OPT_mfp32,
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"fp64");
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}
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void Clang::AddMIPSTargetArgs(const ArgList &Args,
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@ -60,6 +60,18 @@
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// RUN: | FileCheck --check-prefix=CHECK-NOMMSA %s
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// CHECK-NOMMSA: "-target-feature" "-msa"
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//
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// -mfp64
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// RUN: %clang -target mips-linux-gnu -### -c %s \
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// RUN: -mfp32 -mfp64 2>&1 \
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// RUN: | FileCheck --check-prefix=CHECK-MFP64 %s
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// CHECK-MFP64: "-target-feature" "+fp64"
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//
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// -mfp32
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// RUN: %clang -target mips-linux-gnu -### -c %s \
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// RUN: -mfp64 -mfp32 2>&1 \
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// RUN: | FileCheck --check-prefix=CHECK-NOMFP64 %s
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// CHECK-NOMFP64: "-target-feature" "-fp64"
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//
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// -mxgot
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// RUN: %clang -target mips-linux-gnu -### -c %s \
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// RUN: -mno-xgot -mxgot 2>&1 \
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