forked from OSchip/llvm-project
[AMDGPU][MC] Added support of lds_direct operand
See bug 39293: https://bugs.llvm.org/show_bug.cgi?id=39293 Reviewers: artem.tamazov, rampitec Differential Revision: https://reviews.llvm.org/D57889 llvm-svn: 353524
This commit is contained in:
Dmitry Preobrazhensky
parent
01d6bfc94d
commit
942c273d64
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@ -686,6 +686,9 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
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case AMDGPU::XNACK_MASK_HI:
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llvm_unreachable("xnack_mask registers should not be used");
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case AMDGPU::LDS_DIRECT:
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llvm_unreachable("lds_direct register should not be used");
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case AMDGPU::TBA:
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case AMDGPU::TBA_LO:
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case AMDGPU::TBA_HI:
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@ -1095,6 +1095,7 @@ private:
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bool validateMIMGGatherDMask(const MCInst &Inst);
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bool validateMIMGDataSize(const MCInst &Inst);
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bool validateMIMGD16(const MCInst &Inst);
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bool validateLdsDirect(const MCInst &Inst);
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bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
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bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
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unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
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@ -1599,6 +1600,8 @@ static unsigned getSpecialRegForName(StringRef RegName) {
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.Case("vcc", AMDGPU::VCC)
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.Case("flat_scratch", AMDGPU::FLAT_SCR)
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.Case("xnack_mask", AMDGPU::XNACK_MASK)
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.Case("lds_direct", AMDGPU::LDS_DIRECT)
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.Case("src_lds_direct", AMDGPU::LDS_DIRECT)
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.Case("m0", AMDGPU::M0)
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.Case("scc", AMDGPU::SCC)
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.Case("tba", AMDGPU::TBA)
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@ -2465,6 +2468,86 @@ bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
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return true;
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}
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bool AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
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using namespace SIInstrFlags;
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const unsigned Opcode = Inst.getOpcode();
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const MCInstrDesc &Desc = MII.get(Opcode);
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// lds_direct register is defined so that it can be used
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// with 9-bit operands only. Ignore encodings which do not accept these.
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if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0)
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return true;
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const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
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const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
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const int SrcIndices[] = { Src1Idx, Src2Idx };
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// lds_direct cannot be specified as either src1 or src2.
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for (int SrcIdx : SrcIndices) {
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if (SrcIdx == -1) break;
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const MCOperand &Src = Inst.getOperand(SrcIdx);
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if (Src.isReg() && Src.getReg() == LDS_DIRECT) {
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return false;
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}
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}
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if (Src0Idx == -1)
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return true;
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const MCOperand &Src = Inst.getOperand(Src0Idx);
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if (!Src.isReg() || Src.getReg() != LDS_DIRECT)
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return true;
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// lds_direct is specified as src0. Check additional limitations.
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// FIXME: This is a workaround for bug 37943
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// which allows 64-bit VOP3 opcodes use 32-bit operands.
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if (AMDGPU::getRegOperandSize(getMRI(), Desc, Src0Idx) != 4)
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return false;
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// Documentation does not disable lds_direct for SDWA, but SP3 assembler does.
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// FIXME: This inconsistence needs to be investigated further.
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if (Desc.TSFlags & SIInstrFlags::SDWA)
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return false;
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// The following opcodes do not accept lds_direct which is explicitly stated
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// in AMD documentation. However SP3 disables lds_direct for most other 'rev'
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// opcodes as well (e.g. for v_subrev_u32 but not for v_subrev_f32).
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// FIXME: This inconsistence needs to be investigated further.
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switch (Opcode) {
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case AMDGPU::V_LSHLREV_B32_e32_si:
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case AMDGPU::V_LSHLREV_B32_e64_si:
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case AMDGPU::V_LSHLREV_B16_e32_vi:
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case AMDGPU::V_LSHLREV_B16_e64_vi:
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case AMDGPU::V_LSHLREV_B32_e32_vi:
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case AMDGPU::V_LSHLREV_B32_e64_vi:
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case AMDGPU::V_LSHLREV_B64_vi:
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case AMDGPU::V_LSHRREV_B32_e32_si:
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case AMDGPU::V_LSHRREV_B32_e64_si:
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case AMDGPU::V_LSHRREV_B16_e32_vi:
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case AMDGPU::V_LSHRREV_B16_e64_vi:
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case AMDGPU::V_LSHRREV_B32_e32_vi:
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case AMDGPU::V_LSHRREV_B32_e64_vi:
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case AMDGPU::V_LSHRREV_B64_vi:
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case AMDGPU::V_ASHRREV_I32_e64_si:
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case AMDGPU::V_ASHRREV_I32_e32_si:
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case AMDGPU::V_ASHRREV_I16_e32_vi:
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case AMDGPU::V_ASHRREV_I16_e64_vi:
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case AMDGPU::V_ASHRREV_I32_e32_vi:
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case AMDGPU::V_ASHRREV_I32_e64_vi:
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case AMDGPU::V_ASHRREV_I64_vi:
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case AMDGPU::V_PK_LSHLREV_B16_vi:
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case AMDGPU::V_PK_LSHRREV_B16_vi:
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case AMDGPU::V_PK_ASHRREV_I16_vi:
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return false;
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default:
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return true;
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}
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}
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bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
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unsigned Opcode = Inst.getOpcode();
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const MCInstrDesc &Desc = MII.get(Opcode);
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@ -2500,6 +2583,11 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
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bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
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const SMLoc &IDLoc) {
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if (!validateLdsDirect(Inst)) {
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Error(IDLoc,
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"invalid use of lds_direct");
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return false;
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}
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if (!validateSOPLiteral(Inst)) {
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Error(IDLoc,
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"only one literal operand is allowed");
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@ -781,6 +781,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
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// ToDo: no support for execz register
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case 252: break;
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case 253: return createRegOperand(SCC);
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case 254: return createRegOperand(LDS_DIRECT);
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default: break;
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}
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return errOperand(Val, "unknown operand encoding " + Twine(Val));
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@ -268,6 +268,9 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
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case AMDGPU::XNACK_MASK:
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O << "xnack_mask";
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return;
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case AMDGPU::LDS_DIRECT:
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O << "src_lds_direct";
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return;
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case AMDGPU::VCC_LO:
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O << "vcc_lo";
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return;
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@ -163,6 +163,9 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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// Reserve xnack_mask registers - support is not implemented in Codegen.
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reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK);
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// Reserve lds_direct register - support is not implemented in Codegen.
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reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT);
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// Reserve Trap Handler registers - support is not implemented in Codegen.
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reserveRegisterTuples(Reserved, AMDGPU::TBA);
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reserveRegisterTuples(Reserved, AMDGPU::TMA);
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@ -75,6 +75,8 @@ def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>;
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def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>;
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def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>;
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def LDS_DIRECT : SIReg <"lds_direct", 254>;
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def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>;
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def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>;
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@ -409,6 +411,12 @@ def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32,
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let CopyCost = -1;
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}
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def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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(add LDS_DIRECT)> {
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let isAllocatable = 0;
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let CopyCost = -1;
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}
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// Subset of SReg_32 without M0 for SMRD instructions and alike.
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// See comments in SIInstructions.td for more info.
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def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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@ -545,7 +553,7 @@ def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
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}
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def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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(add VGPR_32, SReg_32)> {
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(add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> {
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let isAllocatable = 0;
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}
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@ -0,0 +1,59 @@
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// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9
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//---------------------------------------------------------------------------//
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// lds_direct may be used only with vector ALU instructions
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//---------------------------------------------------------------------------//
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s_and_b32 s2, lds_direct, s1
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// NOGFX9: error
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//---------------------------------------------------------------------------//
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// lds_direct may not be used with V_{LSHL,LSHR,ASHL}REV opcodes
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//---------------------------------------------------------------------------//
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v_ashrrev_i16 v0, lds_direct, v0
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// NOGFX9: error
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v_ashrrev_i32 v0, lds_direct, v0
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// NOGFX9: error
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v_lshlrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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v_lshlrev_b32 v0, lds_direct, v0
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// NOGFX9: error
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v_lshrrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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v_lshrrev_b32 v0, lds_direct, v0
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// NOGFX9: error
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v_pk_ashrrev_i16 v0, lds_direct, v0
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// NOGFX9: error
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v_pk_lshlrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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v_pk_lshrrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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//---------------------------------------------------------------------------//
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// lds_direct cannot be used with 64-bit and larger operands
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//---------------------------------------------------------------------------//
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v_add_f64 v[0:1], lds_direct, v[0:1]
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// NOGFX9: error
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//---------------------------------------------------------------------------//
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// Only SRC0 may specify lds_direct
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//---------------------------------------------------------------------------//
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v_add_i32 v0, v0, lds_direct
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// NOGFX9: error
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v_add_i32 lds_direct, v0, v0
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// NOGFX9: error
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v_fma_f32 v0, v0, v0, lds_direct
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// NOGFX9: error
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@ -0,0 +1,116 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
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//---------------------------------------------------------------------------//
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// VOP1/3
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//---------------------------------------------------------------------------//
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v_mov_b32 v0, src_lds_direct
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// GFX9: v_mov_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x02,0x00,0x7e]
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v_mov_b32_e64 v0, src_lds_direct
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// GFX9: v_mov_b32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
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v_cvt_f64_i32 v[0:1], src_lds_direct
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// GFX9: v_cvt_f64_i32_e32 v[0:1], src_lds_direct ; encoding: [0xfe,0x08,0x00,0x7e]
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v_cvt_f64_i32_e64 v[0:1], src_lds_direct
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// GFX9: v_cvt_f64_i32_e64 v[0:1], src_lds_direct ; encoding: [0x00,0x00,0x44,0xd1,0xfe,0x00,0x00,0x00]
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v_mov_fed_b32 v0, src_lds_direct
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// GFX9: v_mov_fed_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x12,0x00,0x7e]
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v_mov_fed_b32_e64 v0, src_lds_direct
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// GFX9: v_mov_fed_b32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x49,0xd1,0xfe,0x00,0x00,0x00]
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v_fract_f32 v0, src_lds_direct
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// GFX9: v_fract_f32_e32 v0, src_lds_direct ; encoding: [0xfe,0x36,0x00,0x7e]
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v_fract_f32_e64 v0, src_lds_direct
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// GFX9: v_fract_f32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x5b,0xd1,0xfe,0x00,0x00,0x00]
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v_cvt_f16_u16 v0, src_lds_direct
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// GFX9: v_cvt_f16_u16_e32 v0, src_lds_direct ; encoding: [0xfe,0x72,0x00,0x7e]
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//---------------------------------------------------------------------------//
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// VOP2/3
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//---------------------------------------------------------------------------//
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v_cndmask_b32 v0, src_lds_direct, v0, vcc
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// GFX9: v_cndmask_b32_e32 v0, src_lds_direct, v0, vcc ; encoding: [0xfe,0x00,0x00,0x00]
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v_cndmask_b32_e64 v0, src_lds_direct, v0, s[0:1]
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// GFX9: v_cndmask_b32_e64 v0, src_lds_direct, v0, s[0:1] ; encoding: [0x00,0x00,0x00,0xd1,0xfe,0x00,0x02,0x00]
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v_add_f32 v0, src_lds_direct, v0
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// GFX9: v_add_f32_e32 v0, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x02]
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v_add_f32_e64 v0, src_lds_direct, v0
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// GFX9: v_add_f32_e64 v0, src_lds_direct, v0 ; encoding: [0x00,0x00,0x01,0xd1,0xfe,0x00,0x02,0x00]
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v_mul_i32_i24 v0, src_lds_direct, v0
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// GFX9: v_mul_i32_i24_e32 v0, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x0c]
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v_add_co_u32 v0, vcc, src_lds_direct, v0
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// GFX9: v_add_co_u32_e32 v0, vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x32]
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//---------------------------------------------------------------------------//
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// VOP3
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//---------------------------------------------------------------------------//
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v_add_co_u32_e64 v0, s[0:1], src_lds_direct, v0
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// GFX9: v_add_co_u32_e64 v0, s[0:1], src_lds_direct, v0 ; encoding: [0x00,0x00,0x19,0xd1,0xfe,0x00,0x02,0x00]
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v_madmk_f16 v0, src_lds_direct, 0x1121, v0
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// GFX9: v_madmk_f16 v0, src_lds_direct, 0x1121, v0 ; encoding: [0xfe,0x00,0x00,0x48,0x21,0x11,0x00,0x00]
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v_madak_f16 v0, src_lds_direct, v0, 0x1121
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// GFX9: v_madak_f16 v0, src_lds_direct, v0, 0x1121 ; encoding: [0xfe,0x00,0x00,0x4a,0x21,0x11,0x00,0x00]
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v_mad_f32 v0, src_lds_direct, v0, v0
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// GFX9: v_mad_f32 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xc1,0xd1,0xfe,0x00,0x02,0x04]
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v_fma_f32 v0, src_lds_direct, v0, v0
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// GFX9: v_fma_f32 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xcb,0xd1,0xfe,0x00,0x02,0x04]
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v_min3_i16 v0, src_lds_direct, v0, v0
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// GFX9: v_min3_i16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xf5,0xd1,0xfe,0x00,0x02,0x04]
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v_max3_f16 v0, src_lds_direct, v0, v0
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// GFX9: v_max3_f16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xf7,0xd1,0xfe,0x00,0x02,0x04]
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//---------------------------------------------------------------------------//
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// VOP3P
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//---------------------------------------------------------------------------//
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v_pk_mad_i16 v0, src_lds_direct, v0, v0
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// GFX9: v_pk_mad_i16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x40,0x80,0xd3,0xfe,0x00,0x02,0x1c]
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v_pk_add_i16 v0, src_lds_direct, v0
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// GFX9: v_pk_add_i16 v0, src_lds_direct, v0 ; encoding: [0x00,0x00,0x82,0xd3,0xfe,0x00,0x02,0x18]
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//---------------------------------------------------------------------------//
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// VOPC
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//---------------------------------------------------------------------------//
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v_cmp_lt_f16 vcc, src_lds_direct, v0
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// GFX9: v_cmp_lt_f16_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x42,0x7c]
|
||||
|
||||
v_cmp_eq_f32 vcc, src_lds_direct, v0
|
||||
// GFX9: v_cmp_eq_f32_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x84,0x7c]
|
||||
|
||||
v_cmpx_neq_f32 vcc, src_lds_direct, v0
|
||||
// GFX9: v_cmpx_neq_f32_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0xba,0x7c]
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// lds_direct alias
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
v_cmp_lt_f16 vcc, lds_direct, v0
|
||||
// GFX9: v_cmp_lt_f16_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x42,0x7c]
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// FIXME: enable lds_direct for the following opcodes and add tests
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
//v_readfirstlane_b32 s0, src_lds_direct
|
||||
//v_readlane_b32 s0, src_lds_direct, s0
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX9
|
||||
|
||||
# GFX9: v_mov_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x02,0x00,0x7e]
|
||||
0xfe,0x02,0x00,0x7e
|
||||
|
||||
# GFX9: v_mov_b32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
|
||||
0x00,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00
|
||||
|
||||
# GFX9: v_add_f32_e32 v0, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x02]
|
||||
0xfe,0x00,0x00,0x02
|
||||
|
||||
# GFX9: v_pk_mad_i16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x40,0x80,0xd3,0xfe,0x00,0x02,0x1c]
|
||||
0x00,0x40,0x80,0xd3,0xfe,0x00,0x02,0x1c
|
||||
|
||||
# GFX9: v_pk_mul_lo_u16 v0, src_lds_direct, v0 ; encoding: [0x00,0x00,0x81,0xd3,0xfe,0x00,0x02,0x18]
|
||||
0x00,0x00,0x81,0xd3,0xfe,0x00,0x02,0x18
|
||||
|
||||
# GFX9: v_cmpx_le_i32_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0xa6,0x7d]
|
||||
0xfe,0x00,0xa6,0x7d
|
||||
Loading…
Reference in New Issue