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[PowerPC] Add Vector String Isolate instruction definitions and MC Tests 

This patch implements the instruction definition and MC tests for the vector
string isolate instructions.

Differential Revision: https://reviews.llvm.org/D84197
This commit is contained in:
Albion Fung 2020-07-31 11:57:59 -05:00 committed by Amy Kwan
parent 3b0d30ffd3
commit 93fd8dbdc2
3 changed files with 85 additions and 0 deletions
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41
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
View File

@ -59,6 +59,39 @@ class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
string BaseName = "";
}
// VX-Form: [ PO VT R VB RC XO ]
class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<4, OOL, IOL, asmstr, itin> {
bits<5> VT;
bits<5> VB;
bit RC = 0;
let Pattern = pattern;
let Inst{6-10} = VT;
let Inst{11-15} = R;
let Inst{16-20} = VB;
let Inst{21} = RC;
let Inst{22-31} = xo;
}
// Multiclass definition to account for record and non-record form
// instructions of VXRForm.
multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
string asmbase, string asmstr,
InstrItinClass itin, list<dag> pattern> {
let BaseName = asmbase in {
def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)),
itin, pattern>, RecFormRel;
let Defs = [CR6] in
def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
!strconcat(asmbase, !strconcat(". ", asmstr)),
itin, []>, isRecordForm, RecFormRel;
}
}
class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> {
@ -822,6 +855,14 @@ let Predicates = [IsISA3_1] in {
(int_ppc_altivec_vsrdbi v16i8:$VRA,
v16i8:$VRB,
i32:$SH))]>;
defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB),
"vstribr", "$vT, $vB", IIC_VecGeneral, []>;
defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB),
"vstribl", "$vT, $vB", IIC_VecGeneral, []>;
defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB),
"vstrihr", "$vT, $vB", IIC_VecGeneral, []>;
defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB),
"vstrihl", "$vT, $vB", IIC_VecGeneral, []>;
def VINSW :
VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
"vinsw $vD, $rB, $UIM", IIC_VecGeneral,

23
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
View File

@ -459,3 +459,26 @@
# CHECK: xscvsqqp 8, 28
0xfd 0xb 0xe6 0x88
# CHECK: vstribr 2, 2
0x10 0x41 0x10 0x0d
# CHECK: vstribl 2, 2
0x10 0x40 0x10 0x0d
# CHECK: vstrihr 2, 2
0x10 0x43 0x10 0x0d
# CHECK: vstrihl 2, 2
0x10 0x42 0x10 0x0d
# CHECK: vstribr. 2, 2
0x10 0x41 0x14 0x0d
# CHECK: vstribl. 2, 2
0x10 0x40 0x14 0x0d
# CHECK: vstrihr. 2, 2
0x10 0x43 0x14 0x0d
# CHECK: vstrihl. 2, 2
0x10 0x42 0x14 0x0d

21
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
View File

@ -585,3 +585,24 @@
# CHECK-BE: xscvsqqp 8, 28 # encoding: [0xfd,0x0b,0xe6,0x88]
# CHECK-LE: xscvsqqp 8, 28 # encoding: [0x88,0xe6,0x0b,0xfd]
xscvsqqp 8, 28
# CHECK-BE: vstribr 2, 2 # encoding: [0x10,0x41,0x10,0x0d]
# CHECK-LE: vstribr 2, 2 # encoding: [0x0d,0x10,0x41,0x10]
vstribr 2, 2
# CHECK-BE: vstribl 2, 2 # encoding: [0x10,0x40,0x10,0x0d]
# CHECK-LE: vstribl 2, 2 # encoding: [0x0d,0x10,0x40,0x10]
vstribl 2, 2
# CHECK-BE: vstrihr 2, 2 # encoding: [0x10,0x43,0x10,0x0d]
# CHECK-LE: vstrihr 2, 2 # encoding: [0x0d,0x10,0x43,0x10]
vstrihr 2, 2
# CHECK-BE: vstribr. 2, 2 # encoding: [0x10,0x41,0x14,0x0d]
# CHECK-LE: vstribr. 2, 2 # encoding: [0x0d,0x14,0x41,0x10]
vstribr. 2, 2
# CHECK-BE: vstribl. 2, 2 # encoding: [0x10,0x40,0x14,0x0d]
# CHECK-LE: vstribl. 2, 2 # encoding: [0x0d,0x14,0x40,0x10]
vstribl. 2, 2
# CHECK-BE: vstrihr. 2, 2 # encoding: [0x10,0x43,0x14,0x0d]
# CHECK-LE: vstrihr. 2, 2 # encoding: [0x0d,0x14,0x43,0x10]
vstrihr. 2, 2
# CHECK-BE: vstrihl. 2, 2 # encoding: [0x10,0x42,0x14,0x0d]
# CHECK-LE: vstrihl. 2, 2 # encoding: [0x0d,0x14,0x42,0x10]
vstrihl. 2, 2