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[ARM] Use range-based for loops (NFC)

This commit is contained in:
Kazu Hirata 2021-12-20 00:04:52 -08:00
parent 6963be1276
commit 93d79cac2e
6 changed files with 58 additions and 73 deletions
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16
llvm/lib/Target/ARM/A15SDOptimizer.cpp
View File

@ -592,16 +592,15 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
bool Modified = false;
for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
I != E; ++I) {
for (unsigned I : Defs) {
// Follow the def-use chain for this DPR through COPYs, and also through
// PHIs (which are essentially multi-way COPYs). It is because of PHIs that
// we can end up with multiple defs of this DPR.
SmallVector<MachineInstr *, 8> DefSrcs;
if (!Register::isVirtualRegister(*I))
if (!Register::isVirtualRegister(I))
continue;
MachineInstr *Def = MRI->getVRegDef(*I);
MachineInstr *Def = MRI->getVRegDef(I);
if (!Def)
continue;
@ -628,18 +627,17 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
if (NewReg != 0) {
Modified = true;
for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
E = Uses.end(); I != E; ++I) {
for (MachineOperand *Use : Uses) {
// Make sure to constrain the register class of the new register to
// match what we're replacing. Otherwise we can optimize a DPR_VFP2
// reference into a plain DPR, and that will end poorly. NewReg is
// always virtual here, so there will always be a matching subclass
// to find.
MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg()));
LLVM_DEBUG(dbgs() << "Replacing operand " << **I << " with "
LLVM_DEBUG(dbgs() << "Replacing operand " << *Use << " with "
<< printReg(NewReg) << "\n");
(*I)->substVirtReg(NewReg, 0, *TRI);
Use->substVirtReg(NewReg, 0, *TRI);
}
}
Replacements[MI] = NewReg;

7
llvm/lib/Target/ARM/ARMCallingConv.cpp
View File

@ -230,10 +230,9 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT,
unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
if (RegResult) {
for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin();
It != PendingMembers.end(); ++It) {
It->convertToReg(RegResult);
State.addLoc(*It);
for (CCValAssign &PendingMember : PendingMembers) {
PendingMember.convertToReg(RegResult);
State.addLoc(PendingMember);
++RegResult;
}
PendingMembers.clear();

52
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -310,8 +310,7 @@ void ARMConstantIslands::verify() {
BBInfo[RHS.getNumber()].postOffset();
}));
LLVM_DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
CPUser &U = CPUsers[i];
for (CPUser &U : CPUsers) {
unsigned UserOffset = getUserOffset(U);
// Verify offset using the real max displacement without the safety
// adjustment.
@ -481,8 +480,8 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
bool BRChange = false;
for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
BRChange |= fixupImmediateBr(ImmBranches[i]);
for (auto &IB : ImmBranches)
BRChange |= fixupImmediateBr(IB);
if (BRChange && ++NoBRIters > 30)
report_fatal_error("Branch Fix Up pass failed to converge!");
LLVM_DEBUG(dumpBBs());
@ -697,10 +696,9 @@ ARMConstantIslands::findConstPoolEntry(unsigned CPI,
std::vector<CPEntry> &CPEs = CPEntries[CPI];
// Number of entries per constpool index should be small, just do a
// linear search.
for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
if (CPEs[i].CPEMI == CPEMI)
return &CPEs[i];
}
for (CPEntry &CPE : CPEs)
if (CPE.CPEMI == CPEMI)
return &CPE;
return nullptr;
}
@ -1234,27 +1232,27 @@ int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
// No. Look for previously created clones of the CPE that are in range.
unsigned CPI = getCombinedIndex(CPEMI);
std::vector<CPEntry> &CPEs = CPEntries[CPI];
for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
for (CPEntry &CPE : CPEs) {
// We already tried this one
if (CPEs[i].CPEMI == CPEMI)
if (CPE.CPEMI == CPEMI)
continue;
// Removing CPEs can leave empty entries, skip
if (CPEs[i].CPEMI == nullptr)
if (CPE.CPEMI == nullptr)
continue;
if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
U.NegOk)) {
LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
<< CPEs[i].CPI << "\n");
if (isCPEntryInRange(UserMI, UserOffset, CPE.CPEMI, U.getMaxDisp(),
U.NegOk)) {
LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" << CPE.CPI
<< "\n");
// Point the CPUser node to the replacement
U.CPEMI = CPEs[i].CPEMI;
U.CPEMI = CPE.CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (MachineOperand &MO : UserMI->operands())
if (MO.isCPI()) {
MO.setIndex(CPEs[i].CPI);
MO.setIndex(CPE.CPI);
break;
}
// Adjust the refcount of the clone...
CPEs[i].RefCount++;
CPE.RefCount++;
// ...and the original. If we didn't remove the old entry, none of the
// addresses changed, so we don't need another pass.
return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
@ -1675,15 +1673,14 @@ void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
/// are zero.
bool ARMConstantIslands::removeUnusedCPEntries() {
unsigned MadeChange = false;
for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
std::vector<CPEntry> &CPEs = CPEntries[i];
for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
removeDeadCPEMI(CPEs[j].CPEMI);
CPEs[j].CPEMI = nullptr;
MadeChange = true;
}
for (std::vector<CPEntry> &CPEs : CPEntries) {
for (CPEntry &CPE : CPEs) {
if (CPE.RefCount == 0 && CPE.CPEMI) {
removeDeadCPEMI(CPE.CPEMI);
CPE.CPEMI = nullptr;
MadeChange = true;
}
}
}
return MadeChange;
}
@ -1829,8 +1826,7 @@ bool ARMConstantIslands::optimizeThumb2Instructions() {
bool MadeChange = false;
// Shrink ADR and LDR from constantpool.
for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
CPUser &U = CPUsers[i];
for (CPUser &U : CPUsers) {
unsigned Opcode = U.MI->getOpcode();
unsigned NewOpc = 0;
unsigned Scale = 1;

27
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -8400,9 +8400,8 @@ static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
SDLoc DL(Op);
SmallVector<SDValue, 8> VTBLMask;
for (ArrayRef<int>::iterator
I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
for (int I : ShuffleMask)
VTBLMask.push_back(DAG.getConstant(I, DL, MVT::i32));
if (V2.getNode()->isUndef())
return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
@ -10682,25 +10681,23 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
// associated with.
DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2>> CallSiteNumToLPad;
unsigned MaxCSNum = 0;
for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
++BB) {
if (!BB->isEHPad()) continue;
for (MachineBasicBlock &BB : *MF) {
if (!BB.isEHPad())
continue;
// FIXME: We should assert that the EH_LABEL is the first MI in the landing
// pad.
for (MachineBasicBlock::iterator
II = BB->begin(), IE = BB->end(); II != IE; ++II) {
if (!II->isEHLabel()) continue;
for (MachineInstr &II : BB) {
if (!II.isEHLabel())
continue;
MCSymbol *Sym = II->getOperand(0).getMCSymbol();
MCSymbol *Sym = II.getOperand(0).getMCSymbol();
if (!MF->hasCallSiteLandingPad(Sym)) continue;
SmallVectorImpl<unsigned> &CallSiteIdxs = MF->getCallSiteLandingPad(Sym);
for (SmallVectorImpl<unsigned>::iterator
CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
CSI != CSE; ++CSI) {
CallSiteNumToLPad[*CSI].push_back(&*BB);
MaxCSNum = std::max(MaxCSNum, *CSI);
for (unsigned Idx : CallSiteIdxs) {
CallSiteNumToLPad[Idx].push_back(&BB);
MaxCSNum = std::max(MaxCSNum, Idx);
}
break;
}

4
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
View File

@ -1328,8 +1328,8 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
bool Changed = false;
// Process inner loops first.
for (auto I = ML->begin(), E = ML->end(); I != E; ++I)
Changed |= ProcessLoop(*I);
for (MachineLoop *L : *ML)
Changed |= ProcessLoop(L);
LLVM_DEBUG({
dbgs() << "ARM Loops: Processing loop containing:\n";

25
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -137,21 +137,18 @@ public:
int getFPReg() const { return FPReg; }
void emitFnStartLocNotes() const {
for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
FI != FE; ++FI)
Parser.Note(*FI, ".fnstart was specified here");
for (const SMLoc &Loc : FnStartLocs)
Parser.Note(Loc, ".fnstart was specified here");
}
void emitCantUnwindLocNotes() const {
for (Locs::const_iterator UI = CantUnwindLocs.begin(),
UE = CantUnwindLocs.end(); UI != UE; ++UI)
Parser.Note(*UI, ".cantunwind was specified here");
for (const SMLoc &Loc : CantUnwindLocs)
Parser.Note(Loc, ".cantunwind was specified here");
}
void emitHandlerDataLocNotes() const {
for (Locs::const_iterator HI = HandlerDataLocs.begin(),
HE = HandlerDataLocs.end(); HI != HE; ++HI)
Parser.Note(*HI, ".handlerdata was specified here");
for (const SMLoc &Loc : HandlerDataLocs)
Parser.Note(Loc, ".handlerdata was specified here");
}
void emitPersonalityLocNotes() const {
@ -2573,17 +2570,15 @@ public:
void addRegListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const SmallVectorImpl<unsigned> &RegList = getRegList();
for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ++I)
Inst.addOperand(MCOperand::createReg(*I));
for (unsigned Reg : RegList)
Inst.addOperand(MCOperand::createReg(Reg));
}
void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const SmallVectorImpl<unsigned> &RegList = getRegList();
for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ++I)
Inst.addOperand(MCOperand::createReg(*I));
for (unsigned Reg : RegList)
Inst.addOperand(MCOperand::createReg(Reg));
}
void addDPRRegListOperands(MCInst &Inst, unsigned N) const {