forked from OSchip/llvm-project
[SystemZ] Add miscellaneous instructions
This adds a few missing instructions for the assembler and disassembler. Those should be the last missing general- purpose (Chapter 7) instructions for the z10 ISA. llvm-svn: 302667
This commit is contained in:
Ulrich Weigand
parent
4388b071bf
commit
93b369ed11
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@ -1627,6 +1627,9 @@ class ICV<string name>
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// Inherent:
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// One register output operand and no input operands.
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//
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// InherentDual:
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// Two register output operands and no input operands.
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//
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// StoreInherent:
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// One address operand. The instruction stores to the address.
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//
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@ -1752,6 +1755,10 @@ class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
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let R2 = 0;
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}
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class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
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: InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
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mnemonic#"\t$R1, $R2", []>;
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class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
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: InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
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let I2 = value;
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@ -2668,6 +2675,10 @@ class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
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: InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
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mnemonic#"\t$I1, $I2", []>;
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class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
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: InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
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mnemonic#"\t$BD1, $I2", []>;
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class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
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SDPatternOperator operator, Immediate imm>
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: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
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@ -1874,10 +1874,31 @@ let mayLoad = 1, Defs = [CC], Uses = [R0L] in
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let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in
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def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>;
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// Compare and form codeword.
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let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in
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def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>;
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// Update tree.
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let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D],
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Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in
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def UPT : SideEffectInherentE<"upt", 0x0102>;
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// Checksum.
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let mayLoad = 1, Defs = [CC] in
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def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>;
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// Compression call.
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let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in
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def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>;
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// Supervisor call.
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let hasSideEffects = 1, isCall = 1, Defs = [CC] in
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def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>;
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// Monitor call.
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let hasSideEffects = 1, isCall = 1 in
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def MC : SideEffectBinarySI<"mc", 0xAF, imm32zx8>;
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// Store clock.
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let hasSideEffects = 1, Defs = [CC] in {
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def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>;
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@ -1889,10 +1910,18 @@ let hasSideEffects = 1, Defs = [CC] in {
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let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in
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def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>;
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// Extract CPU attribute.
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let hasSideEffects = 1 in
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def ECAG : BinaryRSY<"ecag", 0xEB4C, null_frag, GR64>;
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// Extract CPU time.
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let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in
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def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>;
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// Extract PSW.
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let hasSideEffects = 1, Uses = [CC] in
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def EPSW : InherentDualRRE<"epsw", 0xB98D, GR32>;
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// Execute.
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let hasSideEffects = 1 in {
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def EX : SideEffectBinaryRX<"ex", 0x44, GR64>;
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@ -695,12 +695,27 @@ def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>;
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def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
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// Various complex instructions
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CFC$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>;
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// Move with key
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def : InstRW<[FXa, FXa, FXb, LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
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// Monitor call
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def : InstRW<[FXb], (instregex "MC$")>;
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// Extract CPU attribute
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def : InstRW<[FXb, Lat30], (instregex "ECAG$")>;
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// Extract CPU Time
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def : InstRW<[FXa, Lat5, LSU], (instregex "ECTG$")>;
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// Extract PSW
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def : InstRW<[FXb, Lat30], (instregex "EPSW$")>;
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// Execute
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def : InstRW<[FXb, GroupAlone], (instregex "EX(RL)?$")>;
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@ -628,12 +628,27 @@ def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
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def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
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// Various complex instructions
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CFC$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>;
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// Move with key
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def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
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// Monitor call
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def : InstRW<[FXU], (instregex "MC$")>;
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// Extract CPU attribute
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def : InstRW<[FXU, Lat30], (instregex "ECAG$")>;
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// Extract CPU Time
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def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
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// Extract PSW
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def : InstRW<[FXU, Lat30], (instregex "EPSW$")>;
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// Execute
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def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
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@ -666,12 +666,27 @@ def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
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def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
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// Various complex instructions
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CFC$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>;
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>;
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// Move with key
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def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
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// Monitor call
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def : InstRW<[FXU], (instregex "MC$")>;
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// Extract CPU attribute
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def : InstRW<[FXU, Lat30], (instregex "ECAG$")>;
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// Extract CPU Time
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def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
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// Extract PSW
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def : InstRW<[FXU, Lat30], (instregex "EPSW$")>;
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// Execute
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def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
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@ -1708,6 +1708,24 @@
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# CHECK: celgbr %f15, 0, %r0, 1
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0xb3 0xa0 0x01 0xf0
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# CHECK: cfc 0
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0xb2 0x1a 0x00 0x00
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# CHECK: cfc 0(%r1)
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0xb2 0x1a 0x10 0x00
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# CHECK: cfc 0(%r15)
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0xb2 0x1a 0xf0 0x00
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# CHECK: cfc 4095
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0xb2 0x1a 0x0f 0xff
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# CHECK: cfc 4095(%r1)
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0xb2 0x1a 0x1f 0xff
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# CHECK: cfc 4095(%r15)
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0xb2 0x1a 0xff 0xff
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# CHECK: cfdbr %r0, 0, %f0
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0xb3 0x99 0x00 0x00
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@ -2554,6 +2572,18 @@
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# CHECK: citle %r0, 0
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0xec 0x00 0x00 0x00 0xc0 0x72
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# CHECK: cksm %r0, %r0
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0xb2 0x41 0x00 0x00
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# CHECK: cksm %r0, %r14
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0xb2 0x41 0x00 0x0e
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# CHECK: cksm %r15, %r0
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0xb2 0x41 0x00 0xf0
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# CHECK: cksm %r6, %r8
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0xb2 0x41 0x00 0x68
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# CHECK: cl %r0, 0
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0x55 0x00 0x00 0x00
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@ -3607,6 +3637,18 @@
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# CHECK: cly %r15, 0
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0xe3 0xf0 0x00 0x00 0x00 0x55
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# CHECK: cmpsc %r0, %r0
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0xb2 0x63 0x00 0x00
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# CHECK: cmpsc %r0, %r14
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0xb2 0x63 0x00 0x0e
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# CHECK: cmpsc %r14, %r0
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0xb2 0x63 0x00 0xe0
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# CHECK: cmpsc %r6, %r8
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0xb2 0x63 0x00 0x68
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# CHECK: cp 0(1), 0(1)
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0xf9 0x00 0x00 0x00 0x00 0x00
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@ -4675,6 +4717,45 @@
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# CHECK: ear %r15, %a15
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0xb2 0x4f 0x00 0xff
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# CHECK: ecag %r0, %r0, 0
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0xeb 0x00 0x00 0x00 0x00 0x4c
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# CHECK: ecag %r0, %r15, 0
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0xeb 0x0f 0x00 0x00 0x00 0x4c
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# CHECK: ecag %r14, %r15, 0
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0xeb 0xef 0x00 0x00 0x00 0x4c
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# CHECK: ecag %r15, %r15, 0
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0xeb 0xff 0x00 0x00 0x00 0x4c
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# CHECK: ecag %r0, %r0, -524288
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0xeb 0x00 0x00 0x00 0x80 0x4c
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# CHECK: ecag %r0, %r0, -1
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0xeb 0x00 0x0f 0xff 0xff 0x4c
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# CHECK: ecag %r0, %r0, 0
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0xeb 0x00 0x00 0x00 0x00 0x4c
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# CHECK: ecag %r0, %r0, 1
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0xeb 0x00 0x00 0x01 0x00 0x4c
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# CHECK: ecag %r0, %r0, 524287
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0xeb 0x00 0x0f 0xff 0x7f 0x4c
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# CHECK: ecag %r0, %r0, 0(%r1)
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0xeb 0x00 0x10 0x00 0x00 0x4c
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# CHECK: ecag %r0, %r0, 0(%r15)
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0xeb 0x00 0xf0 0x00 0x00 0x4c
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# CHECK: ecag %r0, %r0, 524287(%r1)
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0xeb 0x00 0x1f 0xff 0x7f 0x4c
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# CHECK: ecag %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0x4c
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# CHECK: ectg 0, 0, %r0
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0xc8 0x01 0x00 0x00 0x00 0x00
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@ -4777,6 +4858,18 @@
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# CHECK: efpc %r15
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0xb3 0x8c 0x00 0xf0
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# CHECK: epsw %r0, %r0
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0xb9 0x8d 0x00 0x00
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# CHECK: epsw %r0, %r15
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0xb9 0x8d 0x00 0x0f
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# CHECK: epsw %r15, %r0
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0xb9 0x8d 0x00 0xf0
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# CHECK: epsw %r6, %r8
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0xb9 0x8d 0x00 0x68
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# CHECK: etnd %r0
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0xb2 0xec 0x00 0x00
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@ -8176,6 +8269,27 @@
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# CHECK: maebr %f15, %f15, %f15
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0xb3 0x0e 0xf0 0xff
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# CHECK: mc 0, 0
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0xaf 0x00 0x00 0x00
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# CHECK: mc 4095, 0
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0xaf 0x00 0x0f 0xff
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# CHECK: mc 0, 255
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0xaf 0xff 0x00 0x00
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# CHECK: mc 0(%r1), 42
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0xaf 0x2a 0x10 0x00
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# CHECK: mc 0(%r15), 42
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0xaf 0x2a 0xf0 0x00
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# CHECK: mc 4095(%r1), 42
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0xaf 0x2a 0x1f 0xff
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# CHECK: mc 4095(%r15), 42
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0xaf 0x2a 0xff 0xff
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# CHECK: mdb %f0, 0
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0xed 0x00 0x00 0x00 0x00 0x1c
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@ -13237,6 +13351,9 @@
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# CHECK: unpku 0(256,%r15), 0
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0xe2 0xff 0xf0 0x00 0x00 0x00
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# CHECK: upt
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0x01 0x02
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# CHECK: x %r0, 0
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0x57 0x00 0x00 0x00
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@ -719,6 +719,17 @@
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celgbr %f0, 0, %r0, 0
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#CHECK: error: invalid operand
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#CHECK: cfc -1
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#CHECK: error: invalid operand
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#CHECK: cfc 4096
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#CHECK: error: invalid use of indexed addressing
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#CHECK: cfc 0(%r1,%r2)
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cfc -1
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cfc 4096
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cfc 0(%r1,%r2)
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#CHECK: error: invalid operand
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#CHECK: cfdbr %r0, -1, %f0
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#CHECK: error: invalid operand
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@ -1116,6 +1127,11 @@
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citno %r0, 0
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cito %r0, 0
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#CHECK: error: invalid register pair
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#CHECK: cksm %r0, %r1
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cksm %r0, %r1
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#CHECK: error: invalid operand
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#CHECK: cl %r0, -1
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#CHECK: error: invalid operand
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@ -1621,6 +1637,14 @@
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cly %r0, -524289
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cly %r0, 524288
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#CHECK: error: invalid register pair
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#CHECK: cmpsc %r1, %r0
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#CHECK: error: invalid register pair
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#CHECK: cmpsc %r0, %r1
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cmpsc %r1, %r0
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cmpsc %r0, %r1
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#CHECK: error: missing length in address
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#CHECK: cp 0, 0(1)
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#CHECK: error: missing length in address
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@ -2143,6 +2167,17 @@
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dxbr %f0, %f2
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dxbr %f2, %f0
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#CHECK: error: invalid operand
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#CHECK: ecag %r0, %r0, -524289
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#CHECK: error: invalid operand
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#CHECK: ecag %r0, %r0, 524288
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#CHECK: error: invalid use of indexed addressing
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#CHECK: ecag %r0, %r0, 0(%r1,%r2)
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ecag %r0, %r0, -524289
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ecag %r0, %r0, 524288
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ecag %r0, %r0, 0(%r1,%r2)
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#CHECK: error: invalid use of indexed addressing
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#CHECK: ectg 160(%r1,%r15),160(%r15), %r2
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#CHECK: error: invalid operand
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@ -3204,6 +3239,23 @@
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maeb %f0, %f0, -1
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maeb %f0, %f0, 4096
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#CHECK: error: invalid operand
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#CHECK: mc -1, 0
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#CHECK: error: invalid operand
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#CHECK: mc 4096, 0
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#CHECK: error: invalid use of indexed addressing
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#CHECK: mc 0(%r1,%r2), 0
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#CHECK: error: invalid operand
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#CHECK: mc 0, -1
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#CHECK: error: invalid operand
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#CHECK: mc 0, 256
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mc -1, 0
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mc 4096, 0
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mc 0(%r1,%r2), 0
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mc 0, -1
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mc 0, 256
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: mdb %f0, -1
|
||||
#CHECK: error: invalid operand
|
||||
|
|
|
|||
|
|
@ -2051,6 +2051,20 @@
|
|||
cegbr %f7, %r8
|
||||
cegbr %f15, %r15
|
||||
|
||||
#CHECK: cfc 0 # encoding: [0xb2,0x1a,0x00,0x00]
|
||||
#CHECK: cfc 0(%r1) # encoding: [0xb2,0x1a,0x10,0x00]
|
||||
#CHECK: cfc 0(%r15) # encoding: [0xb2,0x1a,0xf0,0x00]
|
||||
#CHECK: cfc 4095 # encoding: [0xb2,0x1a,0x0f,0xff]
|
||||
#CHECK: cfc 4095(%r1) # encoding: [0xb2,0x1a,0x1f,0xff]
|
||||
#CHECK: cfc 4095(%r15) # encoding: [0xb2,0x1a,0xff,0xff]
|
||||
|
||||
cfc 0
|
||||
cfc 0(%r1)
|
||||
cfc 0(%r15)
|
||||
cfc 4095
|
||||
cfc 4095(%r1)
|
||||
cfc 4095(%r15)
|
||||
|
||||
#CHECK: cfdbr %r0, 0, %f0 # encoding: [0xb3,0x99,0x00,0x00]
|
||||
#CHECK: cfdbr %r0, 0, %f15 # encoding: [0xb3,0x99,0x00,0x0f]
|
||||
#CHECK: cfdbr %r0, 15, %f0 # encoding: [0xb3,0x99,0xf0,0x00]
|
||||
|
|
@ -3521,6 +3535,16 @@
|
|||
citnl %r15, 1
|
||||
citnh %r15, 1
|
||||
|
||||
#CHECK: cksm %r0, %r8 # encoding: [0xb2,0x41,0x00,0x08]
|
||||
#CHECK: cksm %r0, %r14 # encoding: [0xb2,0x41,0x00,0x0e]
|
||||
#CHECK: cksm %r15, %r0 # encoding: [0xb2,0x41,0x00,0xf0]
|
||||
#CHECK: cksm %r15, %r8 # encoding: [0xb2,0x41,0x00,0xf8]
|
||||
|
||||
cksm %r0, %r8
|
||||
cksm %r0, %r14
|
||||
cksm %r15, %r0
|
||||
cksm %r15, %r8
|
||||
|
||||
#CHECK: cl %r0, 0 # encoding: [0x55,0x00,0x00,0x00]
|
||||
#CHECK: cl %r0, 4095 # encoding: [0x55,0x00,0x0f,0xff]
|
||||
#CHECK: cl %r0, 0(%r1) # encoding: [0x55,0x00,0x10,0x00]
|
||||
|
|
@ -5374,6 +5398,16 @@
|
|||
cly %r0, 524287(%r15,%r1)
|
||||
cly %r15, 0
|
||||
|
||||
#CHECK: cmpsc %r0, %r8 # encoding: [0xb2,0x63,0x00,0x08]
|
||||
#CHECK: cmpsc %r0, %r14 # encoding: [0xb2,0x63,0x00,0x0e]
|
||||
#CHECK: cmpsc %r14, %r0 # encoding: [0xb2,0x63,0x00,0xe0]
|
||||
#CHECK: cmpsc %r14, %r8 # encoding: [0xb2,0x63,0x00,0xe8]
|
||||
|
||||
cmpsc %r0, %r8
|
||||
cmpsc %r0, %r14
|
||||
cmpsc %r14, %r0
|
||||
cmpsc %r14, %r8
|
||||
|
||||
#CHECK: cp 0(1), 0(1) # encoding: [0xf9,0x00,0x00,0x00,0x00,0x00]
|
||||
#CHECK: cp 0(1), 0(1,%r1) # encoding: [0xf9,0x00,0x00,0x00,0x10,0x00]
|
||||
#CHECK: cp 0(1), 0(1,%r15) # encoding: [0xf9,0x00,0x00,0x00,0xf0,0x00]
|
||||
|
|
@ -6461,6 +6495,34 @@
|
|||
ear %r7, %a8
|
||||
ear %r15, %a15
|
||||
|
||||
#CHECK: ecag %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x4c]
|
||||
#CHECK: ecag %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x4c]
|
||||
#CHECK: ecag %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x4c]
|
||||
#CHECK: ecag %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x4c]
|
||||
#CHECK: ecag %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x4c]
|
||||
#CHECK: ecag %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x4c]
|
||||
#CHECK: ecag %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x4c]
|
||||
#CHECK: ecag %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x4c]
|
||||
#CHECK: ecag %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x4c]
|
||||
#CHECK: ecag %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x4c]
|
||||
#CHECK: ecag %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x4c]
|
||||
#CHECK: ecag %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x4c]
|
||||
#CHECK: ecag %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x4c]
|
||||
|
||||
ecag %r0,%r0,0
|
||||
ecag %r0,%r15,0
|
||||
ecag %r14,%r15,0
|
||||
ecag %r15,%r15,0
|
||||
ecag %r0,%r0,-524288
|
||||
ecag %r0,%r0,-1
|
||||
ecag %r0,%r0,0
|
||||
ecag %r0,%r0,1
|
||||
ecag %r0,%r0,524287
|
||||
ecag %r0,%r0,0(%r1)
|
||||
ecag %r0,%r0,0(%r15)
|
||||
ecag %r0,%r0,524287(%r1)
|
||||
ecag %r0,%r0,524287(%r15)
|
||||
|
||||
#CHECK: ectg 0, 0, %r0 # encoding: [0xc8,0x01,0x00,0x00,0x00,0x00]
|
||||
#CHECK: ectg 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x00,0xf0,0x00]
|
||||
#CHECK: ectg 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x01,0xf0,0x00]
|
||||
|
|
@ -6535,6 +6597,16 @@
|
|||
efpc %r1
|
||||
efpc %r15
|
||||
|
||||
#CHECK: epsw %r0, %r8 # encoding: [0xb9,0x8d,0x00,0x08]
|
||||
#CHECK: epsw %r0, %r15 # encoding: [0xb9,0x8d,0x00,0x0f]
|
||||
#CHECK: epsw %r15, %r0 # encoding: [0xb9,0x8d,0x00,0xf0]
|
||||
#CHECK: epsw %r15, %r8 # encoding: [0xb9,0x8d,0x00,0xf8]
|
||||
|
||||
epsw %r0, %r8
|
||||
epsw %r0, %r15
|
||||
epsw %r15, %r0
|
||||
epsw %r15, %r8
|
||||
|
||||
#CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00]
|
||||
#CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff]
|
||||
#CHECK: ex %r0, 0(%r1) # encoding: [0x44,0x00,0x10,0x00]
|
||||
|
|
@ -8766,6 +8838,22 @@
|
|||
maebr %f7, %f8, %f9
|
||||
maebr %f15, %f15, %f15
|
||||
|
||||
#CHECK: mc 0, 0 # encoding: [0xaf,0x00,0x00,0x00]
|
||||
#CHECK: mc 4095, 0 # encoding: [0xaf,0x00,0x0f,0xff]
|
||||
#CHECK: mc 0, 255 # encoding: [0xaf,0xff,0x00,0x00]
|
||||
#CHECK: mc 0(%r1), 42 # encoding: [0xaf,0x2a,0x10,0x00]
|
||||
#CHECK: mc 0(%r15), 42 # encoding: [0xaf,0x2a,0xf0,0x00]
|
||||
#CHECK: mc 4095(%r1), 42 # encoding: [0xaf,0x2a,0x1f,0xff]
|
||||
#CHECK: mc 4095(%r15), 42 # encoding: [0xaf,0x2a,0xff,0xff]
|
||||
|
||||
mc 0, 0
|
||||
mc 4095, 0
|
||||
mc 0, 255
|
||||
mc 0(%r1), 42
|
||||
mc 0(%r15), 42
|
||||
mc 4095(%r1), 42
|
||||
mc 4095(%r15), 42
|
||||
|
||||
#CHECK: mdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1c]
|
||||
#CHECK: mdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1c]
|
||||
#CHECK: mdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1c]
|
||||
|
|
@ -12317,6 +12405,10 @@
|
|||
unpku 0(256,%r1), 0
|
||||
unpku 0(256,%r15), 0
|
||||
|
||||
#CHECK: upt # encoding: [0x01,0x02]
|
||||
|
||||
upt
|
||||
|
||||
#CHECK: x %r0, 0 # encoding: [0x57,0x00,0x00,0x00]
|
||||
#CHECK: x %r0, 4095 # encoding: [0x57,0x00,0x0f,0xff]
|
||||
#CHECK: x %r0, 0(%r1) # encoding: [0x57,0x00,0x10,0x00]
|
||||
|
|
|
|||
Loading…
Reference in New Issue