forked from OSchip/llvm-project
[AArch64] Move add_and_or_is_add pattern. NFC
This just moves the add_and_or_is_add further up in the file, so that it can be shared with SVE as in D128159.
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@ -734,6 +734,22 @@ def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
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def AArch64mrs : SDNode<"AArch64ISD::MRS",
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def AArch64mrs : SDNode<"AArch64ISD::MRS",
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SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
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SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
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[SDNPHasChain, SDNPOutGlue]>;
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[SDNPHasChain, SDNPOutGlue]>;
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// Match add node and also treat an 'or' node is as an 'add' if the or'ed operands
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// have no common bits.
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def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
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[(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
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if (N->getOpcode() == ISD::ADD)
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return true;
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return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
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}]> {
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let GISelPredicateCode = [{
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// Only handle G_ADD for now. FIXME. build capability to compute whether
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// operands of G_OR have common bits set or not.
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return MI.getOpcode() == TargetOpcode::G_ADD;
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}];
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -6473,22 +6489,6 @@ def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
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VectorIndexS:$idx)),
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VectorIndexS:$idx)),
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(SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
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(SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
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// Match add node and also treat an 'or' node is as an 'add' if the or'ed operands
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// have no common bits.
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def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
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[(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
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if (N->getOpcode() == ISD::ADD)
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return true;
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return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
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}]> {
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let GISelPredicateCode = [{
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// Only handle G_ADD for now. FIXME. build capability to compute whether
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// operands of G_OR have common bits set or not.
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return MI.getOpcode() == TargetOpcode::G_ADD;
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}];
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}
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// AdvSIMD scalar shift instructions
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// AdvSIMD scalar shift instructions
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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