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This patch implements ei and di instructions for mips. Test cases are added. 

llvm-svn: 188176
This commit is contained in:
Vladimir Medic 2013-08-12 13:07:23 +00:00
parent 467ddb161c
commit 939877ee14
3 changed files with 49 additions and 2 deletions
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18
llvm/lib/Target/Mips/MipsInstrFormats.td
View File

@ -520,6 +520,24 @@ class ER_FM<bits<6> funct>
let Inst{5-0} = funct;
}
//===----------------------------------------------------------------------===//
// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
//===----------------------------------------------------------------------===//
class EI_FM<bits<1> sc>
{
bits<32> Inst;
bits<5> rt;
let Inst{31-26} = 0x10;
let Inst{25-21} = 0xb;
let Inst{20-16} = rt;
let Inst{15-11} = 0xc;
let Inst{10-6} = 0;
let Inst{5} = sc;
let Inst{4-0} = 0;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

13
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -660,6 +660,11 @@ class ER_FT<string opstr> :
InstSE<(outs), (ins),
opstr, [], NoItinerary, FrmOther>;
// Interrupts
class DEI_FT<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rt), (ins),
!strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
// Sync
let hasSideEffects = 1 in
class SYNC_FT :
@ -953,7 +958,8 @@ defm LBu : LoadM<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
defm LH : LoadM<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
LW_FM<0x21>;
defm LHu : LoadM<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
defm LW : LoadM<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>;
defm LW : LoadM<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
LW_FM<0x23>;
defm SB : StoreM<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
defm SH : StoreM<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
defm SW : StoreM<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
@ -973,6 +979,9 @@ def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
def ERET : ER_FT<"eret">, ER_FM<0x18>;
def DERET : ER_FT<"deret">, ER_FM<0x1f>;
def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
/// Load-linked, Store-conditional
let Predicates = [NotN64, HasStdEnc] in {
def LL : LLBase<"ll", GPR32Opnd, mem>, LW_FM<0x30>;
@ -1145,6 +1154,8 @@ def : InstAlias<"syscall", (SYSCALL 0), 1>;
def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
def : InstAlias<"break", (BREAK 0, 0), 1>;
def : InstAlias<"ei", (EI ZERO), 1>;
def : InstAlias<"di", (DI ZERO), 1>;
//===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//

20
llvm/test/MC/Mips/mips-control-instructions.s
View File

@ -10,6 +10,12 @@
# CHECK32: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]
# CHECK32: eret # encoding: [0x42,0x00,0x00,0x18]
# CHECK32: deret # encoding: [0x42,0x00,0x00,0x1f]
# CHECK32: di # encoding: [0x41,0x60,0x60,0x00]
# CHECK32: di # encoding: [0x41,0x60,0x60,0x00]
# CHECK32: di $10 # encoding: [0x41,0x6a,0x60,0x00]
# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK32: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
# CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
@ -18,7 +24,12 @@
# CHECK64: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]
# CHECK64: eret # encoding: [0x42,0x00,0x00,0x18]
# CHECK64: deret # encoding: [0x42,0x00,0x00,0x1f]
# CHECK64: di # encoding: [0x41,0x60,0x60,0x00]
# CHECK64: di # encoding: [0x41,0x60,0x60,0x00]
# CHECK64: di $10 # encoding: [0x41,0x6a,0x60,0x00]
# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
# CHECK64: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
break
break 7
break 7,5
@ -26,3 +37,10 @@
syscall 0x3454
eret
deret
di
di $0
di $10
ei
ei $0
ei $10