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Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ExpandPostRAPseudos and mark them as pseudos in the td file. 

llvm-svn: 165302
This commit is contained in:
Craig Topper 2012-10-05 06:05:15 +00:00
parent 766e7277ed
commit 9384902ef1
3 changed files with 17 additions and 19 deletions
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24
llvm/lib/Target/X86/X86InstrCompiler.td
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@ -230,25 +230,19 @@ def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
IIC_ALU_NONMEM>; IIC_ALU_NONMEM>;
// Use sbb to materialize carry bit. // Use sbb to materialize carry bit.
let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in { let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1 in {
// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
// However, Pat<> can't replicate the destination reg into the inputs of the // However, Pat<> can't replicate the destination reg into the inputs of the
// result. // result.
// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
// X86CodeEmitter. [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "", def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
[(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))], [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
IIC_ALU_NONMEM>;
def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
[(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
IIC_ALU_NONMEM>,
OpSize; OpSize;
def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "", def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
[(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))], [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
IIC_ALU_NONMEM>; def SETB_C64r : RI<0, Pseudo, (outs GR64:$dst), (ins), "",
def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "", [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
[(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
IIC_ALU_NONMEM>;
} // isCodeGenOnly } // isCodeGenOnly

8
llvm/lib/Target/X86/X86InstrInfo.cpp
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@ -3509,6 +3509,14 @@ static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
case X86::SETB_C8r:
return Expand2AddrUndef(MI, get(X86::SBB8rr));
case X86::SETB_C16r:
return Expand2AddrUndef(MI, get(X86::SBB16rr));
case X86::SETB_C32r:
return Expand2AddrUndef(MI, get(X86::SBB32rr));
case X86::SETB_C64r:
return Expand2AddrUndef(MI, get(X86::SBB64rr));
case X86::V_SET0: case X86::V_SET0:
case X86::FsFLD0SS: case X86::FsFLD0SS:
case X86::FsFLD0SD: case X86::FsFLD0SD:

4
llvm/lib/Target/X86/X86MCInstLower.cpp
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@ -371,10 +371,6 @@ ReSimplify:
case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break; case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break; case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break; case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break; case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break; case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;