forked from OSchip/llvm-project
[ARM][MachineOutliner] Emit more CFI instructions
This patch make the outliner emit CFI instructions in a few more places: * after LR is restored, but before the return in an outlined function * around save/restore of LR to/from a register at calls to outlined functions * around save/restore of LR to/from the stack at calls to outlined functions The latter two only when the function does NOT spill LR. If the function spills LR, then outliner generated saves/restores around calls are not considered interesting for unwinding the frame. Differential Revision: https://reviews.llvm.org/D89483
This commit is contained in:
Momchil Velikov
parent
bbc3e03032
commit
937ab6a785
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@ -6071,7 +6071,7 @@ ARMBaseInstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
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}
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void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &It) const {
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MachineBasicBlock::iterator It) const {
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unsigned Opc = Subtarget.isThumb() ? ARM::t2STR_PRE : ARM::STR_PRE_IMM;
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int Align = -Subtarget.getStackAlignment().value();
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BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::SP)
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@ -6081,8 +6081,45 @@ void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
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.add(predOps(ARMCC::AL));
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}
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void ARMBaseInstrInfo::emitCFIForLRSaveOnStack(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
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MachineFunction &MF = *MBB.getParent();
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const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
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unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
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int Align = Subtarget.getStackAlignment().value();
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// Add a CFI saying the stack was moved down.
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int64_t StackPosEntry =
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MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Align));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(StackPosEntry)
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.setMIFlags(MachineInstr::FrameSetup);
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// Add a CFI saying that the LR that we want to find is now higher than
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// before.
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int64_t LRPosEntry =
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MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfLR, -Align));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(LRPosEntry)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator It,
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Register Reg) const {
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MachineFunction &MF = *MBB.getParent();
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const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
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unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
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unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
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int64_t LRPosEntry = MF.addFrameInst(
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MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(LRPosEntry)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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void ARMBaseInstrInfo::restoreLRFromStack(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator &It) const {
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MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
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unsigned Opc = Subtarget.isThumb() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
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MachineInstrBuilder MIB = BuildMI(MBB, It, DebugLoc(), get(Opc), ARM::LR)
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.addReg(ARM::SP, RegState::Define)
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@ -6092,6 +6129,39 @@ void ARMBaseInstrInfo::restoreLRFromStack(
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MIB.addImm(Subtarget.getStackAlignment().value()).add(predOps(ARMCC::AL));
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}
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void ARMBaseInstrInfo::emitCFIForLRRestoreFromStack(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
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// Now stack has moved back up...
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MachineFunction &MF = *MBB.getParent();
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const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
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unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
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int64_t StackPosEntry =
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MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(StackPosEntry)
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.setMIFlags(MachineInstr::FrameDestroy);
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// ... and we have restored LR.
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int64_t LRPosEntry =
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MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(LRPosEntry)
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.setMIFlags(MachineInstr::FrameDestroy);
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}
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void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
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MachineFunction &MF = *MBB.getParent();
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const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
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unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
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int64_t LRPosEntry =
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MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(LRPosEntry)
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.setMIFlags(MachineInstr::FrameDestroy);
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}
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void ARMBaseInstrInfo::buildOutlinedFrame(
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MachineBasicBlock &MBB, MachineFunction &MF,
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const outliner::OutlinedFunction &OF) const {
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@ -6133,28 +6203,11 @@ void ARMBaseInstrInfo::buildOutlinedFrame(
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// Insert a save before the outlined region
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saveLROnStack(MBB, It);
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unsigned StackAlignment = Subtarget.getStackAlignment().value();
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const TargetSubtargetInfo &STI = MF.getSubtarget();
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const MCRegisterInfo *MRI = STI.getRegisterInfo();
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unsigned DwarfReg = MRI->getDwarfRegNum(ARM::LR, true);
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// Add a CFI saying the stack was moved down.
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int64_t StackPosEntry = MF.addFrameInst(
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MCCFIInstruction::cfiDefCfaOffset(nullptr, StackAlignment));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(StackPosEntry)
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.setMIFlags(MachineInstr::FrameSetup);
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// Add a CFI saying that the LR that we want to find is now higher than
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// before.
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int64_t LRPosEntry = MF.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, DwarfReg, StackAlignment));
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BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
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.addCFIIndex(LRPosEntry)
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.setMIFlags(MachineInstr::FrameSetup);
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emitCFIForLRSaveOnStack(MBB, It);
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// Insert a restore before the terminator for the function. Restore LR.
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restoreLRFromStack(MBB, Et);
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emitCFIForLRRestoreFromStack(MBB, Et);
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}
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// If this is a tail call outlined function, then there's already a return.
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@ -6204,6 +6257,7 @@ MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
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return It;
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}
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const ARMFunctionInfo &AFI = *C.getMF()->getInfo<ARMFunctionInfo>();
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// Can we save to a register?
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if (C.CallConstructionID == MachineOutlinerRegSave) {
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unsigned Reg = findRegisterToSaveLRTo(C);
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@ -6211,15 +6265,23 @@ MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
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// Save and restore LR from that register.
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copyPhysReg(MBB, It, DebugLoc(), Reg, ARM::LR, true);
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if (!AFI.isLRSpilled())
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emitCFIForLRSaveToReg(MBB, It, Reg);
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CallPt = MBB.insert(It, CallMIB);
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copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true);
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if (!AFI.isLRSpilled())
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emitCFIForLRRestoreFromReg(MBB, It);
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It--;
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return CallPt;
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}
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// We have the default case. Save and restore from SP.
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saveLROnStack(MBB, It);
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if (!AFI.isLRSpilled())
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emitCFIForLRSaveOnStack(MBB, It);
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CallPt = MBB.insert(It, CallMIB);
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restoreLRFromStack(MBB, It);
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if (!AFI.isLRSpilled())
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emitCFIForLRRestoreFromStack(MBB, It);
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It--;
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return CallPt;
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}
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@ -368,12 +368,33 @@ private:
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// Adds an instruction which saves the link register on top of the stack into
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/// the MachineBasicBlock \p MBB at position \p It.
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void saveLROnStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &It) const;
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MachineBasicBlock::iterator It) const;
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/// Adds an instruction which restores the link register from the top the
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/// stack into the MachineBasicBlock \p MBB at position \p It.
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void restoreLRFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &It) const;
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MachineBasicBlock::iterator It) const;
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/// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
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/// for the case when the LR is saved on the stack.
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void emitCFIForLRSaveOnStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator It) const;
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/// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
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/// for the case when the LR is saved in the register \p Reg.
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void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator It,
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Register Reg) const;
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/// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
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/// after the LR is was restored from the stack.
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void emitCFIForLRRestoreFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator It) const;
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/// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
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/// after the LR is was restored from a register.
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void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator It) const;
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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@ -295,7 +295,7 @@ body: |
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; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr
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; CHECK: early-clobber $sp = STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8
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; CHECK: BL @bar, implicit-def dead $lr, implicit $sp
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; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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@ -320,7 +320,7 @@ body: |
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; CHECK: liveins: $r11, $r10, $r9, $r8, $r7, $r6, $r5, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr
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; CHECK: early-clobber $sp = STR_PRE_IMM killed $lr, $sp, -8, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8
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; CHECK: BL @bar, implicit-def dead $lr, implicit $sp
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; CHECK: $r0 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
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@ -335,7 +335,7 @@ body: |
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; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr
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; CHECK: early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8
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; CHECK: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp
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; CHECK: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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@ -348,7 +348,7 @@ body: |
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; CHECK: liveins: $r11, $r10, $r9, $r8, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8, $lr
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; CHECK: early-clobber $sp = t2STR_PRE killed $lr, $sp, -8, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -8
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; CHECK: tBL 14 /* CC::al */, $noreg, @bar, implicit-def dead $lr, implicit $sp
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; CHECK: $r0 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = t2MOVi 2, 14 /* CC::al */, $noreg, $noreg
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@ -0,0 +1,78 @@
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; RUN: llc --verify-machineinstrs --force-dwarf-frame-section %s -o - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7m-unknown-unknown-eabi"
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; Derived from
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; volatile int a, b, c, d, e, f, g, h;
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;
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; int x() {
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; int r = (a + b) / (c + d) + e + f;
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; return r + 1;
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; }
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;
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;
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; int y() {
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; int r = (a + b) / (c + d) + e + f;
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; return r + 2;
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; }
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; Checks that CFI instruction are emitted around saves/restores of
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; the LR on stack.
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@a = dso_local global i32 0, align 4
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@b = dso_local global i32 0, align 4
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@c = dso_local global i32 0, align 4
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@d = dso_local global i32 0, align 4
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@e = dso_local global i32 0, align 4
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@f = dso_local global i32 0, align 4
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define dso_local i32 @x() local_unnamed_addr #0 {
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entry:
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%0 = load volatile i32, i32* @a, align 4
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%1 = load volatile i32, i32* @b, align 4
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%add = add nsw i32 %1, %0
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%2 = load volatile i32, i32* @c, align 4
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%3 = load volatile i32, i32* @d, align 4
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%add1 = add nsw i32 %3, %2
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%div = sdiv i32 %add, %add1
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%4 = load volatile i32, i32* @e, align 4
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%5 = load volatile i32, i32* @f, align 4
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%add2 = add i32 %div, 1
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%add3 = add i32 %add2, %4
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%add4 = add i32 %add3, %5
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ret i32 %add4
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}
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; CHECK-LABEL: x:
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; CHECK: str lr, [sp, #-8]!
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: .cfi_offset lr, -8
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: ldr lr, [sp], #8
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: .cfi_restore lr
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define dso_local i32 @y() local_unnamed_addr #0 {
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entry:
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%0 = load volatile i32, i32* @a, align 4
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%1 = load volatile i32, i32* @b, align 4
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%add = add nsw i32 %1, %0
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%2 = load volatile i32, i32* @c, align 4
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%3 = load volatile i32, i32* @d, align 4
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%add1 = add nsw i32 %3, %2
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%div = sdiv i32 %add, %add1
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%4 = load volatile i32, i32* @e, align 4
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%5 = load volatile i32, i32* @f, align 4
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%add2 = add i32 %div, 2
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%add3 = add i32 %add2, %4
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%add4 = add i32 %add3, %5
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ret i32 %add4
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}
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; CHECK-LABEL: y:
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; CHECK: str lr, [sp, #-8]!
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: .cfi_offset lr, -8
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: ldr lr, [sp], #8
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: .cfi_restore lr
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attributes #0 = { minsize nofree norecurse nounwind optsize }
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@ -0,0 +1,73 @@
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; RUN: llc --verify-machineinstrs --force-dwarf-frame-section %s -o - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7m-unknown-unknown-eabi"
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; Derived from
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; volatile int a, b, c, d, e, f, g, h;
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;
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; int x() {
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; int r = a + b + c + d + e + f;
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; return r + 1;
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; }
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;
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;
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; int y() {
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; int r = a + b + c + d + e + f;
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; return r + 2;
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; }
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; Check CFI instructions when LR is saved/restored to/from a register.
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@a = dso_local global i32 0, align 4
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@b = dso_local global i32 0, align 4
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@c = dso_local global i32 0, align 4
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@d = dso_local global i32 0, align 4
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@e = dso_local global i32 0, align 4
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@f = dso_local global i32 0, align 4
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define dso_local i32 @x() local_unnamed_addr #0 {
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entry:
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%0 = load volatile i32, i32* @a, align 4
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%1 = load volatile i32, i32* @b, align 4
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%2 = load volatile i32, i32* @c, align 4
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%3 = load volatile i32, i32* @d, align 4
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%4 = load volatile i32, i32* @e, align 4
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%5 = load volatile i32, i32* @f, align 4
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%add = add i32 %0, 1
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%add1 = add i32 %add, %1
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%add2 = add i32 %add1, %2
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%add3 = add i32 %add2, %3
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%add4 = add i32 %add3, %4
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%add5 = add i32 %add4, %5
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ret i32 %add5
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}
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; CHECK-LABEL: x:
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; CHECK: mov r3, lr
|
||||
; CHECK-NEXT: .cfi_register lr, r3
|
||||
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
|
||||
; CHECK-NEXT: mov lr, r3
|
||||
; CHECK-NEXT: .cfi_restore lr
|
||||
|
||||
define dso_local i32 @y() local_unnamed_addr #0 {
|
||||
entry:
|
||||
%0 = load volatile i32, i32* @a, align 4
|
||||
%1 = load volatile i32, i32* @b, align 4
|
||||
%2 = load volatile i32, i32* @c, align 4
|
||||
%3 = load volatile i32, i32* @d, align 4
|
||||
%4 = load volatile i32, i32* @e, align 4
|
||||
%5 = load volatile i32, i32* @f, align 4
|
||||
%add = add i32 %0, 2
|
||||
%add1 = add i32 %add, %1
|
||||
%add2 = add i32 %add1, %2
|
||||
%add3 = add i32 %add2, %3
|
||||
%add4 = add i32 %add3, %4
|
||||
%add5 = add i32 %add4, %5
|
||||
ret i32 %add5
|
||||
}
|
||||
; CHECK-LABEL: y:
|
||||
; CHECK: mov r3, lr
|
||||
; CHECK-NEXT: .cfi_register lr, r3
|
||||
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
|
||||
; CHECK-NEXT: mov lr, r3
|
||||
; CHECK-NEXT: .cfi_restore lr
|
||||
|
||||
attributes #0 = { minsize nofree norecurse nounwind optsize }
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
; RUN: llc --verify-machineinstrs --force-dwarf-frame-section %s -o - | FileCheck %s
|
||||
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
target triple = "thumbv7m-unknown-unknown-eabi"
|
||||
|
||||
; Derived from
|
||||
; __attribute__((noinline)) int h(int a, int b) { return a + b; }
|
||||
;
|
||||
; int f(int a, int b, int c, int d) {
|
||||
; if (a < 0)
|
||||
; return -1;
|
||||
; a = h(a, b);
|
||||
; return 2 + a * (a + b) / (c + d);
|
||||
; }
|
||||
;
|
||||
; int g(int a, int b, int c, int d) {
|
||||
; if (a < 0)
|
||||
; return -1;
|
||||
; a = h(a, b);
|
||||
; return 1 + a * (a + b) / (c + d);
|
||||
; }
|
||||
; Check CFI instructions inside the outlined function.
|
||||
|
||||
define dso_local i32 @h(i32 %a, i32 %b) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%add = add nsw i32 %b, %a
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
define dso_local i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #1 {
|
||||
entry:
|
||||
%cmp = icmp slt i32 %a, 0
|
||||
br i1 %cmp, label %return, label %if.end
|
||||
|
||||
if.end: ; preds = %entry
|
||||
%call = tail call i32 @h(i32 %a, i32 %b) #2
|
||||
%add = add nsw i32 %call, %b
|
||||
%mul = mul nsw i32 %add, %call
|
||||
%add1 = add nsw i32 %d, %c
|
||||
%div = sdiv i32 %mul, %add1
|
||||
%add2 = add nsw i32 %div, 2
|
||||
br label %return
|
||||
|
||||
return: ; preds = %entry, %if.end
|
||||
%retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
|
||||
ret i32 %retval.0
|
||||
}
|
||||
|
||||
define dso_local i32 @g(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #1 {
|
||||
entry:
|
||||
%cmp = icmp slt i32 %a, 0
|
||||
br i1 %cmp, label %return, label %if.end
|
||||
|
||||
if.end: ; preds = %entry
|
||||
%call = tail call i32 @h(i32 %a, i32 %b) #2
|
||||
%add = add nsw i32 %call, %b
|
||||
%mul = mul nsw i32 %add, %call
|
||||
%add1 = add nsw i32 %d, %c
|
||||
%div = sdiv i32 %mul, %add1
|
||||
%add2 = add nsw i32 %div, 1
|
||||
br label %return
|
||||
|
||||
return: ; preds = %entry, %if.end
|
||||
%retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
|
||||
ret i32 %retval.0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: OUTLINED_FUNCTION_0:
|
||||
; CHECK: str lr, [sp, #-8]!
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 8
|
||||
; CHECK-NEXT: .cfi_offset lr, -8
|
||||
; CHECK: ldr lr, [sp], #8
|
||||
; CHECK-NEXT: .cfi_def_cfa_offset 0
|
||||
; CHECK-NEXT: .cfi_restore lr
|
||||
; CHECK-NEXT: bx lr
|
||||
|
||||
attributes #0 = { minsize noinline norecurse nounwind optsize readnone }
|
||||
attributes #1 = { minsize norecurse nounwind optsize readnone }
|
||||
attributes #2 = { minsize optsize }
|
||||
Loading…
Reference in New Issue