maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RISCV] Extend 32-bit test coverage of neg-abs tests for D91120

This commit is contained in:
Simon Pilgrim 2020-11-19 13:59:18 +00:00
parent fceaff41d6
commit 9374e7b178
1 changed files with 48 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
llvm/test/CodeGen/RISCV/neg-abs.ll
View File

@ -1,17 +1,55 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs \ ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32-unknown-unknown | FileCheck %s --check-prefix=RV32
; RUN: -mtriple=riscv64-unknown-unknown < %s | FileCheck %s ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64-unknown-unknown | FileCheck %s --check-prefix=RV64
declare i32 @llvm.abs.i32(i32, i1 immarg)
declare i64 @llvm.abs.i64(i64, i1 immarg) declare i64 @llvm.abs.i64(i64, i1 immarg)
define i64@neg_abs(i64 %x) { define i32 @neg_abs32(i32 %x) {
; CHECK-LABEL: neg_abs: ; RV32-LABEL: neg_abs32:
; CHECK: # %bb.0: ; RV32: # %bb.0:
; CHECK-NEXT: srai a1, a0, 63 ; RV32-NEXT: srai a1, a0, 31
; CHECK-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; CHECK-NEXT: xor a0, a0, a1 ; RV32-NEXT: xor a0, a0, a1
; CHECK-NEXT: neg a0, a0 ; RV32-NEXT: neg a0, a0
; CHECK-NEXT: ret ; RV32-NEXT: ret
;
; RV64-LABEL: neg_abs32:
; RV64: # %bb.0:
; RV64-NEXT: sext.w a1, a0
; RV64-NEXT: srai a1, a1, 63
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: negw a0, a0
; RV64-NEXT: ret
%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
%neg = sub nsw i32 0, %abs
ret i32 %neg
}
define i64 @neg_abs64(i64 %x) {
; RV32-LABEL: neg_abs64:
; RV32: # %bb.0:
; RV32-NEXT: bgez a1, .LBB1_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: snez a2, a0
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: neg a1, a1
; RV32-NEXT: neg a0, a0
; RV32-NEXT: .LBB1_2:
; RV32-NEXT: snez a2, a0
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: neg a1, a1
; RV32-NEXT: neg a0, a0
; RV32-NEXT: ret
;
; RV64-LABEL: neg_abs64:
; RV64: # %bb.0:
; RV64-NEXT: srai a1, a0, 63
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: neg a0, a0
; RV64-NEXT: ret
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
%neg = sub nsw i64 0, %abs %neg = sub nsw i64 0, %abs
ret i64 %neg ret i64 %neg