forked from OSchip/llvm-project
[AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF
This adds legalization for scalar G_CTTZ and G_CTTZ_ZERO_UNDEF. Vector support requires handling vector G_BITREVERSE, which I haven't gotten around to yet. For G_CTTZ_ZERO_UNDEF, we just lower it to G_CTTZ. For G_CTTZ, we match SelectionDAG's lowering to a G_BITREVERSE + G_CTLZ. e.g. https://godbolt.org/z/nPEseYh1s (With this patch, we have slightly worse codegen than SDAG for types smaller than s32; it seems like we're missing a combine.) Also, this adds in a function to build G_BITREVERSE to MachineIRBuilder. Differential Revision: https://reviews.llvm.org/D104065
This commit is contained in:
Jessica Paquette
parent
4f6ec382c8
commit
933df6ca79
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@ -1868,6 +1868,11 @@ public:
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return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
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}
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/// Build and insert \p Dst = G_BITREVERSE \p Src
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MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src) {
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return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
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}
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virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
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ArrayRef<SrcOp> SrcOps,
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Optional<unsigned> Flags = None);
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@ -672,6 +672,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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// TODO: Custom lowering for v2s32, v4s32, v2s64.
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getActionDefinitionsBuilder(G_BITREVERSE).legalFor({s32, s64, v8s8, v16s8});
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getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).lower();
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// TODO: Handle vector types.
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getActionDefinitionsBuilder(G_CTTZ)
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.clampScalar(0, s32, s64)
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.scalarSameSizeAs(1, 0)
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.customFor({s32, s64});
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getActionDefinitionsBuilder(G_SHUFFLE_VECTOR)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &DstTy = Query.Types[0];
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@ -790,6 +798,8 @@ bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
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return legalizeCTPOP(MI, MRI, Helper);
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case TargetOpcode::G_ATOMIC_CMPXCHG:
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return legalizeAtomicCmpxchg128(MI, MRI, Helper);
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case TargetOpcode::G_CTTZ:
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return legalizeCTTZ(MI, Helper);
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}
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llvm_unreachable("expected switch to return");
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@ -1157,3 +1167,14 @@ bool AArch64LegalizerInfo::legalizeAtomicCmpxchg128(
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MI.eraseFromParent();
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return true;
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}
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bool AArch64LegalizerInfo::legalizeCTTZ(MachineInstr &MI,
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LegalizerHelper &Helper) const {
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MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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LLT Ty = MRI.getType(MI.getOperand(1).getReg());
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auto BitReverse = MIRBuilder.buildBitReverse(Ty, MI.getOperand(1));
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MIRBuilder.buildCTLZ(MI.getOperand(0).getReg(), BitReverse);
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MI.eraseFromParent();
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return true;
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}
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@ -56,6 +56,7 @@ private:
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LegalizerHelper &Helper) const;
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bool legalizeAtomicCmpxchg128(MachineInstr &MI, MachineRegisterInfo &MRI,
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LegalizerHelper &Helper) const;
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bool legalizeCTTZ(MachineInstr &MI, LegalizerHelper &Helper) const;
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const AArch64Subtarget *ST;
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};
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} // End llvm namespace.
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@ -0,0 +1,94 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
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...
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---
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name: s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s8
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; CHECK: liveins: $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[C1]]
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
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; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
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; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
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; CHECK: $w0 = COPY %ext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%val:_(s8) = G_IMPLICIT_DEF
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%cttz:_(s8) = G_CTTZ_ZERO_UNDEF %val(s8)
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%ext:_(s32) = G_ANYEXT %cttz(s8)
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$w0 = COPY %ext(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: s16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s16
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; CHECK: liveins: $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[C1]]
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
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; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
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; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
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; CHECK: $w0 = COPY %ext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%val:_(s16) = G_IMPLICIT_DEF
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%cttz:_(s16) = G_CTTZ_ZERO_UNDEF %val(s16)
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%ext:_(s32) = G_ANYEXT %cttz(s16)
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$w0 = COPY %ext(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s32
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; CHECK: liveins: $w0
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; CHECK: %val:_(s32) = COPY $w0
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE %val
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; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
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; CHECK: $w0 = COPY [[CTLZ]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%val:_(s32) = COPY $w0
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%1:_(s32) = G_CTTZ_ZERO_UNDEF %val(s32)
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$w0 = COPY %1(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: s64
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; CHECK: liveins: $x0
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; CHECK: %val:_(s64) = COPY $x0
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE %val
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; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
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; CHECK: $x0 = COPY [[CTLZ]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%val:_(s64) = COPY $x0
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%1:_(s64) = G_CTTZ_ZERO_UNDEF %val(s64)
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$x0 = COPY %1(s64)
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RET_ReallyLR implicit $x0
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...
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@ -0,0 +1,92 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
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...
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---
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name: s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s8
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; CHECK: liveins: $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[C1]]
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
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; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
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; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
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; CHECK: $w0 = COPY %ext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%val:_(s8) = G_IMPLICIT_DEF
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%cttz:_(s8) = G_CTTZ %val(s8)
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%ext:_(s32) = G_ANYEXT %cttz(s8)
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$w0 = COPY %ext(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: s16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s16
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; CHECK: liveins: $w0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
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; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[C]], [[C1]]
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
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; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
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; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
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; CHECK: $w0 = COPY %ext(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%val:_(s16) = G_IMPLICIT_DEF
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%cttz:_(s16) = G_CTTZ %val(s16)
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%ext:_(s32) = G_ANYEXT %cttz(s16)
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$w0 = COPY %ext(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s32
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; CHECK: liveins: $w0
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; CHECK: %val:_(s32) = COPY $w0
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE %val
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; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
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; CHECK: $w0 = COPY [[CTLZ]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%val:_(s32) = COPY $w0
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%1:_(s32) = G_CTTZ %val(s32)
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$w0 = COPY %1(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: s64
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; CHECK: liveins: $x0
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; CHECK: %val:_(s64) = COPY $x0
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE %val
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; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
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; CHECK: $x0 = COPY [[CTLZ]](s64)
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; CHECK: RET_ReallyLR implicit $x0
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%val:_(s64) = COPY $x0
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%1:_(s64) = G_CTTZ %val(s64)
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$x0 = COPY %1(s64)
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RET_ReallyLR implicit $x0
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@ -540,11 +540,11 @@
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_CTTZ_ZERO_UNDEF (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_CTLZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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