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Revert "GlobalISel/AArch64: don't optimize away redundant branches at -O0" 

This reverts commit 458c230b5e.

This broke LLDB buildbot testcase where breakpoint set at start of loop
failed to hit. https://lab.llvm.org/buildbot/#/builders/96/builds/9404

https://github.com/llvm/llvm-project/blob/main/lldb/test/API/commands/process/attach/main.cpp#L15

Differential Revision: https://reviews.llvm.org/D105238
This commit is contained in:
Muhammad Omair Javaid 2021-07-09 08:11:08 +05:00
parent 2e194dec60
commit 932e3d9960
10 changed files with 26 additions and 127 deletions
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2
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
View File

@ -566,7 +566,7 @@ bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
if (BrInst.isUnconditional()) {
// If the unconditional target is the layout successor, fallthrough.
if (OptLevel == CodeGenOpt::None || !CurMBB.isLayoutSuccessor(Succ0MBB))
if (!CurMBB.isLayoutSuccessor(Succ0MBB))
MIRBuilder.buildBr(*Succ0MBB);
// Link successors.

13
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
View File

@ -2093,8 +2093,17 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) {
I.eraseFromParent();
return true;
}
case TargetOpcode::G_BR:
return false;
case TargetOpcode::G_BR: {
// If the branch jumps to the fallthrough block, don't bother emitting it.
// Only do this for -O0 for a good code size improvement, because when
// optimizations are enabled we want to leave this choice to
// MachineBlockPlacement.
bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::None;
if (EnableOpt || !MBB.isLayoutSuccessor(I.getOperand(0).getMBB()))
return false;
I.eraseFromParent();
return true;
}
case TargetOpcode::G_SHL:
return earlySelectSHL(I, MRI);
case TargetOpcode::G_CONSTANT: {

24
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
View File

@ -329,7 +329,6 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB6_1
; CHECK-NOLSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB6_2 Depth 2
@ -354,8 +353,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB6_1
; CHECK-NOLSE-O0-NEXT: b LBB6_5
; CHECK-NOLSE-O0-NEXT: LBB6_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: ret
@ -379,7 +377,6 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: ldr w8, [x0]
; CHECK-LSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-LSE-O0-NEXT: b LBB6_1
; CHECK-LSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-LSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Folded Reload
@ -393,8 +390,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-LSE-O0-NEXT: cset w8, eq
; CHECK-LSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB6_1
; CHECK-LSE-O0-NEXT: b LBB6_2
; CHECK-LSE-O0-NEXT: LBB6_2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-LSE-O0-NEXT: ret
@ -422,7 +418,6 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB7_1
; CHECK-NOLSE-O0-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB7_2 Depth 2
@ -447,8 +442,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB7_1
; CHECK-NOLSE-O0-NEXT: b LBB7_5
; CHECK-NOLSE-O0-NEXT: LBB7_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: ret
@ -472,7 +466,6 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: ldr x8, [x0]
; CHECK-LSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: b LBB7_1
; CHECK-LSE-O0-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-LSE-O0-NEXT: ldr x8, [sp, #24] ; 8-byte Folded Reload
@ -486,8 +479,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
; CHECK-LSE-O0-NEXT: cset w8, eq
; CHECK-LSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB7_1
; CHECK-LSE-O0-NEXT: b LBB7_2
; CHECK-LSE-O0-NEXT: LBB7_2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-LSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-LSE-O0-NEXT: ret
@ -515,7 +507,6 @@ define i32 @fetch_and_or(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB8_1
; CHECK-NOLSE-O0-NEXT: LBB8_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB8_2 Depth 2
@ -540,8 +531,7 @@ define i32 @fetch_and_or(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB8_1
; CHECK-NOLSE-O0-NEXT: LBB8_5
; CHECK-NOLSE-O0-NEXT: LBB8_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: ret
@ -580,7 +570,6 @@ define i64 @fetch_and_or_64(i64* %p) #0 {
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: b LBB9_1
; CHECK-NOLSE-O0-NEXT: LBB9_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB9_2 Depth 2
@ -604,8 +593,7 @@ define i64 @fetch_and_or_64(i64* %p) #0 {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str x9, [sp, #24] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB9_1
; CHECK-NOLSE-O0-NEXT: b LBB9_5
; CHECK-NOLSE-O0-NEXT: LBB9_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
; CHECK-NOLSE-O0-NEXT: ret

3
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View File

@ -87,6 +87,8 @@ bb2:
; CHECK: body:
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
; We don't emit a branch here, as we can fallthrough to the successor.
; CHECK-NOT: G_BR
; CHECK: [[END]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
define void @uncondbr_fallthrough() {
@ -135,6 +137,7 @@ false:
; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
; Make sure we have one successor
; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)
; CHECK-NOT: G_BR
;
; Check basic block L1 has 2 successors: BBL1 and BBL2
; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (address-taken):

3
llvm/test/CodeGen/AArch64/unwind-preserved.ll
View File

@ -365,8 +365,7 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; GISEL-NEXT: bl may_throw_neon
; GISEL-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; GISEL-NEXT: .Ltmp4:
; GISEL-NEXT: b .LBB1_1
; GISEL-NEXT: .LBB1_1: // %.Lcontinue
; GISEL-NEXT: // %bb.1: // %.Lcontinue
; GISEL-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; GISEL-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
; GISEL-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload

10
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
View File

@ -55,9 +55,8 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_6: # %sw.default
; MIPS32-NEXT: j $BB0_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_7: # %sw.epilog
; MIPS32-NEXT: .insn
; MIPS32-NEXT: # %bb.7: # %sw.epilog
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ori $3, $zero, 8
@ -159,9 +158,8 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_6: # %sw.default
; MIPS32_PIC-NEXT: b $BB0_7
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_7: # %sw.epilog
; MIPS32_PIC-NEXT: .insn
; MIPS32_PIC-NEXT: # %bb.7: # %sw.epilog
; MIPS32_PIC-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: ori $3, $zero, 8

16
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
View File

@ -57,8 +57,6 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32*
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
@ -95,8 +93,6 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32*
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
@ -248,8 +244,6 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* %
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_9: # %b.PHI.1
; MIPS32-NEXT: lw $2, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
@ -288,8 +282,6 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* %
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
@ -440,8 +432,6 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB2_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
@ -478,8 +468,6 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB2_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
@ -632,8 +620,6 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 0($1)
; MIPS32-NEXT: swc1 $f0, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB3_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_9: # %b.PHI.1
; MIPS32-NEXT: lwc1 $f0, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
@ -672,8 +658,6 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 0($1)
; MIPS32-NEXT: swc1 $f0, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB3_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 4($sp) # 4-byte Folded Reload

16
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
View File

@ -57,8 +57,6 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64*
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB0_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 32($sp) # 8-byte Folded Reload
@ -95,8 +93,6 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64*
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB0_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
@ -254,8 +250,6 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: sw $2, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_9: # %b.PHI.1
; MIPS32-NEXT: lw $2, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
@ -305,8 +299,6 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 8($sp) # 4-byte Folded Reload
@ -471,8 +463,6 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB2_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 32($sp) # 8-byte Folded Reload
@ -509,8 +499,6 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB2_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
@ -665,8 +653,6 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a,
; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 40($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB3_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_9: # %b.PHI.1
; MIPS32-NEXT: ldc1 $f0, 80($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
@ -705,8 +691,6 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a,
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB3_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload

18
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
View File

@ -22,8 +22,6 @@ define i1 @phi_i1(i1 %cnd, i1 %a, i1 %b) {
; MIPS32-NEXT: $BB0_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 16
@ -64,8 +62,6 @@ define i8 @phi_i8(i1 %cnd, i8 %a, i8 %b) {
; MIPS32-NEXT: $BB1_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 16
@ -106,8 +102,6 @@ define i16 @phi_i16(i1 %cnd, i16 %a, i16 %b) {
; MIPS32-NEXT: $BB2_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB2_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 16
@ -148,8 +142,6 @@ define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
; MIPS32-NEXT: $BB3_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB3_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 16
@ -200,8 +192,6 @@ define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) {
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB4_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB4_4: # %cond.end
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
@ -246,8 +236,6 @@ define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b,
; MIPS32-NEXT: $BB5_3: # %cond.false
; MIPS32-NEXT: ldc1 $f0, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB5_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB5_4: # %cond.end
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
@ -293,8 +281,6 @@ define float @phi_float(i1 %cnd, float %a, float %b) {
; MIPS32-NEXT: $BB6_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB6_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB6_4: # %cond.end
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: mtc1 $1, $f0
@ -339,8 +325,6 @@ define void @phi_ambiguous_float_in_gpr(i1 %cnd, float* %f32_ptr_a, float* %f32_
; MIPS32-NEXT: $BB7_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB7_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB7_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload
@ -388,8 +372,6 @@ define double @phi_double(double %a, double %b, i1 %cnd) {
; MIPS32-NEXT: $BB8_3: # %cond.false
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB8_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB8_4: # %cond.end
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24

48
llvm/test/DebugInfo/AArch64/fallthrough-branch.ll
View File

@ -1,48 +0,0 @@
; RUN: llc -O0 -stop-before=livedebugvalues < %s | FileCheck %s
; ModuleID = '/tmp/t.o'
source_filename = "/tmp/t.o"
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-macosx11.0.0"
define swiftcc void @"$s1t1f1bySb_tF"(i1 %0) !dbg !35 {
%2 = alloca i1, align 8
%3 = bitcast i1* %2 to i8*
call void @llvm.memset.p0i8.i64(i8* align 8 %3, i8 0, i64 1, i1 false)
store i1 %0, i1* %2, align 8, !dbg !37
; CHECK: B %bb.1, debug-location !{{[0-9]+}}
br i1 %0, label %4, label %5, !dbg !38
4: ; preds = %1
; Check that at -O0 the branches and their debug locations are not eliminated.
; CHECK: B %bb.3, debug-location !{{[0-9]+}}
br label %6, !dbg !39
5: ; preds = %1
; CHECK: B %bb.3, debug-location !{{[0-9]+}}
br label %6, !dbg !40
6: ; preds = %4, %5
ret void, !dbg !39
}
; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg) #1
attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly }
!llvm.module.flags = !{!6, !7, !14}
!llvm.dbg.cu = !{!15, !27}
!6 = !{i32 7, !"Dwarf Version", i32 4}
!7 = !{i32 2, !"Debug Info Version", i32 3}
!14 = !{i32 1, !"Swift Version", i32 7}
!15 = distinct !DICompileUnit(language: DW_LANG_Swift, file: !16, producer: "Swift", emissionKind: LineTablesOnly)
!16 = !DIFile(filename: "t.swift", directory: "/tmp")
!17 = !{}
!27 = distinct !DICompileUnit(language: DW_LANG_ObjC, file: !16, emissionKind: LineTablesOnly)
!35 = distinct !DISubprogram(name: "f", linkageName: "$s1t1f1bySb_tF", scope: !15, file: !16, line: 1, type: !36, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !15, retainedNodes: !17)
!36 = !DISubroutineType(types: null)
!37 = !DILocation(line: 0, scope: !35)
!38 = !DILocation(line: 2, column: 9, scope: !35)
!39 = !DILocation(line: 3, column: 1, scope: !35)
!40 = !DILocation(line: 2, column: 18, scope: !35)