forked from OSchip/llvm-project
Don't mark CMOV_GR8 as two-address, or commutable, since it's a pseudo.
llvm-svn: 80271
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@ -1034,19 +1034,19 @@ let isTwoAddress = 1 in {
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// Conditional moves
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// Conditional moves
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let Uses = [EFLAGS] in {
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let Uses = [EFLAGS] in {
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let isCommutable = 1 in {
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// X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to
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// X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// however that requires promoting the operands, and can induce additional
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// however that requires promoting the operands, and can induce additional
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// i8 register pressure.
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// i8 register pressure.
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let usesCustomDAGSchedInserter = 1 in
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let usesCustomDAGSchedInserter = 1, isTwoAddress = 0 in
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def CMOV_GR8 : I<0, Pseudo,
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def CMOV_GR8 : I<0, Pseudo,
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(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
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(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
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"#CMOV_GR8 PSEUDO!",
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"#CMOV_GR8 PSEUDO!",
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[(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
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[(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
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imm:$cond, EFLAGS))]>;
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imm:$cond, EFLAGS))]>;
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let isCommutable = 1 in {
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def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
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def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"cmovb\t{$src2, $dst|$dst, $src2}",
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"cmovb\t{$src2, $dst|$dst, $src2}",
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