forked from OSchip/llvm-project
[LegalizeTypes] Only expand CTLZ/CTTZ/CTPOP during type promotion if the new type is legal.
We might be promoting a large non-power of 2 type and the new type may need to be split. Once we split it we may have a ctlz/cttz/ctpop instruction for the split type. I'm also concerned that we may create large shifts with shift amounts that are too small.
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@ -586,7 +586,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
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// If the larger CTLZ isn't supported by the target, try to expand now.
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// If we expand later we'll end up with more operations since we lost the
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// original type.
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if (!OVT.isVector() &&
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if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
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!TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ, NVT) &&
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!TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ_ZERO_UNDEF, NVT)) {
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if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
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@ -614,7 +614,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
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// original type.
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// TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
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// TargetLowering.
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if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() &&
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if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(NVT) &&
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!TLI.isOperationLegalOrCustomOrPromote(ISD::CTPOP, NVT)) {
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if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
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Result = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Result);
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@ -636,7 +636,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
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// If the larger CTTZ isn't supported by the target, try to expand now.
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// If we expand later we'll end up with more operations since we lost the
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// original type.
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if (!OVT.isVector() &&
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if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
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!TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ, NVT) &&
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!TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ_ZERO_UNDEF, NVT)) {
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if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
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