forked from OSchip/llvm-project
[mips] Fix disassembly of [ls][wd]c[23], cache, and pref
Fixes PR21015, and PR20993.
Patch by Jun Koi
llvm-svn: 218745
This commit is contained in:
Daniel Sanders
parent
7072a7968f
commit
92db6b78f7
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@ -250,6 +250,11 @@ static DecodeStatus DecodeMem(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCacheOp(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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@ -267,6 +272,14 @@ static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -964,6 +977,23 @@ static DecodeStatus DecodeMem(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCacheOp(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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unsigned Hint = fieldFromInstruction(Insn, 16, 5);
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unsigned Base = fieldFromInstruction(Insn, 21, 5);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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Inst.addOperand(MCOperand::CreateImm(Hint));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
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@ -1067,6 +1097,42 @@ static DecodeStatus DecodeFMem(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFMem2(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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unsigned Reg = fieldFromInstruction(Insn, 16, 5);
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unsigned Base = fieldFromInstruction(Insn, 21, 5);
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Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFMem3(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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unsigned Reg = fieldFromInstruction(Insn, 16, 5);
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unsigned Base = fieldFromInstruction(Insn, 21, 5);
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Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -178,6 +178,38 @@ class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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let mayStore = 1;
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}
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class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
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InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
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let DecoderMethod = "DecodeFMem2";
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let mayStore = 1;
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}
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class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
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InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
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let DecoderMethod = "DecodeFMem2";
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let mayLoad = 1;
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}
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class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
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InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
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let DecoderMethod = "DecodeFMem3";
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let mayStore = 1;
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}
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class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> :
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InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
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let DecoderMethod = "DecodeFMem3";
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let mayLoad = 1;
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}
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class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
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@ -407,24 +439,24 @@ def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
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// Cop2 Memory Instructions
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// FIXME: These aren't really FPU instructions and as such don't belong in this
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// file
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def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
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def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
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ISA_MIPS1_NOT_32R6_64R6;
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def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
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def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
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ISA_MIPS1_NOT_32R6_64R6;
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def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
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def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
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ISA_MIPS2_NOT_32R6_64R6;
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def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
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def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
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ISA_MIPS2_NOT_32R6_64R6;
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// Cop3 Memory Instructions
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// FIXME: These aren't really FPU instructions and as such don't belong in this
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// file
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let DecoderNamespace = "COP3_" in {
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def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
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def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
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def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
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def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
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def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
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def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
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ISA_MIPS2;
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def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
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def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
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ISA_MIPS2;
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}
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@ -1415,13 +1415,15 @@ def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
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def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
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def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
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class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> :
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class CacheOp<string instr_asm, Operand MemOpnd> :
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InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
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!strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>;
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!strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther> {
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let DecoderMethod = "DecodeCacheOp";
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}
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def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>,
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def CACHE : CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
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INSN_MIPS3_32_NOT_32R6_64R6;
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def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>,
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def PREF : CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
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INSN_MIPS3_32_NOT_32R6_64R6;
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//===----------------------------------------------------------------------===//
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@ -0,0 +1,13 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips2 | FileCheck %s
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# CHECK: sdc3 $5, 9154($6)
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0xfc 0xc5 0x23 0xc2
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# CHECK: swc3 $6, 9158($7)
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0xec 0xe6 0x23 0xc6
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# CHECK: ldc3 $7, 9162($8)
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0xdd 0x07 0x23 0xca
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# CHECK: lwc3 $8, 9166($9)
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0xcd 0x28 0x23 0xce
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@ -1,4 +1,5 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux | FileCheck %s
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# CHECK: abs.d $f12, $f14
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0x46 0x20 0x73 0x05
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@ -436,3 +437,15 @@
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# CHECK: rdhwr $5, $29
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# CHECK: .set pop
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0x7c 0x05 0xe8 0x3b
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# CHECK: cache 1, 2($3)
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0xbc 0x61 0x00 0x02
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# CHECK: pref 3, 4($2)
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0xcc 0x43 0x00 0x04
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# CHECK: swc2 $9, 9158($7)
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0xe8 0xe9 0x23 0xc6
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# CHECK: lwc2 $8, 9162($6)
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0xc8 0xc8 0x23 0xca
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@ -85,3 +85,9 @@
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# CHECK: sdxc1 $f8, $4($25)
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0x4f 0x24 0x40 0x09
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# CHECK: sdc2 $9, 9158($7)
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0xf8 0xe9 0x23 0xc6
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# CHECK: ldc2 $3, 9162($8)
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0xd9 0x03 0x23 0xca
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