forked from OSchip/llvm-project
parent
d2e89190d9
commit
92c95f812d
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@ -165,9 +165,8 @@ static TypeClass getClass (const Type *T) {
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void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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Constant *C, unsigned R) {
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if (C->getType()->isIntegral()) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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unsigned Class = getClass(C->getType());
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unsigned Class = getClass(C->getType());
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ConstantInt *CI = cast<ConstantInt>(C);
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switch (Class) {
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switch (Class) {
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case cByte:
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case cByte:
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
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@ -185,12 +184,12 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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return;
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return;
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}
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}
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default:
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default:
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assert (0 && "Can't move this kind of constant");
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assert (0 && "Can't copy this kind of constant into register yet");
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return;
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return;
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}
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}
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}
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}
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assert (0 && "Can't copy constants into registers yet");
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assert (0 && "Can't copy this kind of constant into register yet");
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}
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}
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bool V8ISel::runOnFunction(Function &Fn) {
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bool V8ISel::runOnFunction(Function &Fn) {
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@ -246,6 +245,9 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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case Instruction::Add:
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case Instruction::Add:
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BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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break;
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case Instruction::Sub:
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BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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break;
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default:
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default:
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visitInstruction (I);
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visitInstruction (I);
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return;
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return;
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@ -62,7 +62,7 @@ def CALL : InstV8 {
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let Name = "call";
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let Name = "call";
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}
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}
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// Section B.9 - SETHI Instruction, p. 102
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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def SETHIi: F2_1<0b100, "sethi">;
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// Section B.11 - Logical Instructions, p. 106
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// Section B.11 - Logical Instructions, p. 106
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@ -78,6 +78,9 @@ def SRAri : F3_1<2, 0b100111, "sra">;
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// Section B.13 - Add Instructions, p. 108
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000, "add">;
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def ADDrr : F3_1<2, 0b000000, "add">;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100, "sub">;
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// Section B.25 - Jump and Link, p. 126
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// Section B.25 - Jump and Link, p. 126
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def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
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def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
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def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
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def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
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