forked from OSchip/llvm-project
Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT node
is lowered properly and covers everything LowerSELECT_CC did. Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This avoid the ugly instruction by instruction checking in printOperand. Added a swap instruction present in the allegrex core. Added two conditional instructions present in the allegrex core : MOVZ and MOVN. They both allow a more efficient SELECT operation for integers. Also added SELECT patterns to optimize MOVZ and MOVN usage. The brcond and setcc patterns were cleaned: redundant and suboptimal patterns were removed. The suboptimals were replaced by more efficient ones. Fixed some instructions that were using immZExt16 instead of immSExt16. llvm-svn: 54724
This commit is contained in:
Bruno Cardoso Lopes
parent
703a64c38d
commit
92c64ae2d0
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@ -62,6 +62,7 @@ namespace {
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode);
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void printOperand(const MachineInstr *MI, int opNum);
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void printUnsignedImm(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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void printFCCOperand(const MachineInstr *MI, int opNum,
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@ -383,11 +384,7 @@ printOperand(const MachineInstr *MI, int opNum)
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break;
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case MachineOperand::MO_Immediate:
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if ((MI->getOpcode() == Mips::SLTiu) || (MI->getOpcode() == Mips::ORi) ||
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(MI->getOpcode() == Mips::LUi) || (MI->getOpcode() == Mips::ANDi))
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O << (unsigned short int)MO.getImm();
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else
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O << (short int)MO.getImm();
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O << (short int)MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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@ -407,7 +404,6 @@ printOperand(const MachineInstr *MI, int opNum)
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<< '_' << MO.getIndex();
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break;
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// FIXME: Verify correct
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case MachineOperand::MO_ConstantPoolIndex:
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O << TAI->getPrivateGlobalPrefix() << "CPI"
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<< getFunctionNumber() << "_" << MO.getIndex();
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@ -420,6 +416,16 @@ printOperand(const MachineInstr *MI, int opNum)
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if (closeP) O << ")";
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}
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void MipsAsmPrinter::
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printUnsignedImm(const MachineInstr *MI, int opNum)
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{
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const MachineOperand &MO = MI->getOperand(opNum);
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if (MO.getType() == MachineOperand::MO_Immediate)
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O << (unsigned short int)MO.getImm();
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else
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printOperand(MI, opNum);
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}
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void MipsAsmPrinter::
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printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier)
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{
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@ -46,6 +46,7 @@ getTargetNodeName(unsigned Opcode) const
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::GPRel : return "MipsISD::GPRel";
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case MipsISD::Ret : return "MipsISD::Ret";
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case MipsISD::CMov : return "MipsISD::CMov";
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case MipsISD::SelectCC : return "MipsISD::SelectCC";
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case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
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case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
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@ -99,7 +100,6 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::SELECT, MVT::f32, Custom);
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setOperationAction(ISD::SELECT, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SETCC, MVT::f32, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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@ -120,8 +120,6 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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@ -149,6 +147,9 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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if (!Subtarget->hasBitCount())
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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if (!Subtarget->hasSwap())
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setStackPointerRegisterToSaveRestore(Mips::SP);
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computeRegisterProperties();
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}
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@ -176,7 +177,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG)
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case ISD::OR: return LowerANDOR(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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}
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return SDValue();
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@ -450,31 +450,23 @@ LowerSELECT(SDValue Op, SelectionDAG &DAG)
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SDValue True = Op.getOperand(1);
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SDValue False = Op.getOperand(2);
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// if the incomming condition comes from fpcmp, the select
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// operation must use FPSelectCC, otherwise SelectCC.
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if (Cond.getOpcode() != MipsISD::FPCmp)
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// if the incomming condition comes from a integer compare, the select
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// operation must be SelectCC or a conditional move if the subtarget
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// supports it.
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if (Cond.getOpcode() != MipsISD::FPCmp) {
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if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
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return Op;
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return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
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Cond, True, False);
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}
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// if the incomming condition comes from fpcmp, the select
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// operation must use FPSelectCC.
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SDValue CCNode = Cond.getOperand(2);
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return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
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Cond, True, False, CCNode);
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}
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SDValue MipsTargetLowering::
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LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
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{
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue True = Op.getOperand(2);
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SDValue False = Op.getOperand(3);
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SDValue CC = Op.getOperand(4);
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SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
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return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
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SetCCRes, True, False);
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}
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SDValue MipsTargetLowering::
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LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
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{
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@ -40,6 +40,9 @@ namespace llvm {
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// Conditional Move
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CMov,
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// Select CC Pseudo Instruction
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SelectCC,
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@ -99,7 +102,6 @@ namespace llvm {
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
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@ -21,6 +21,9 @@ def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
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SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
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def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
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SDTCisInt<4>]>;
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def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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@ -48,11 +51,16 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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// Select Condition Code
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def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
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// Conditional Move
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def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
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def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
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def HasSwap : Predicate<"Subtarget.hasSwap()">;
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def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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@ -61,10 +69,14 @@ def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
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// Instruction operand types
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def uimm16 : Operand<i32>;
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def simm16 : Operand<i32>;
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def shamt : Operand<i32>;
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// Unsigned Operand
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def uimm16 : Operand<i32> {
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let PrintMethod = "printUnsignedImm";
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}
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// Address operand
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def mem : Operand<i32> {
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let PrintMethod = "printMemOperand";
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@ -143,6 +155,14 @@ class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd=0 in
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class MArithR<bits<6> func, string instr_asm> :
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@ -352,6 +372,18 @@ class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
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// Byte Swap
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class ByteSwap<bits<6> func, string instr_asm>:
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FR< 0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
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// Conditional Move
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class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
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FR< 0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
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CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
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[(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
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CPURegs:$cond, MovCode))], NoItinerary>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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@ -402,10 +434,10 @@ def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
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def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
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def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
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def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
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def ANDi : LogicI<0x0c, "andi", and>;
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def ORi : LogicI<0x0d, "ori", or>;
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def XORi : LogicI<0x0e, "xori", xor>;
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@ -495,8 +527,23 @@ let Predicates = [HasSEInReg] in {
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/// Count Leading
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let Predicates = [HasBitCount] in {
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def CLZ : CountLeading<0b010110, "clz", ctlz>;
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//def CLO : CountLeading<0b010110, "clo">;
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let rt = 0 in
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def CLZ : CountLeading<0b010110, "clz", ctlz>;
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}
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/// Byte Swap
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let Predicates = [HasSwap] in {
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let shamt = 0x3, rs = 0 in
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def WSBW : ByteSwap<0x20, "wsbw">;
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}
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/// Conditional Move
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def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
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def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
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let Predicates = [HasCondMov], isTwoAddress = 1 in {
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def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
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def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
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}
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/// No operation
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@ -573,55 +620,65 @@ def : Pat<(not CPURegs:$in),
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(NOR CPURegs:$in, ZERO)>;
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// extended load and stores
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def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
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def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
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def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
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def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
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def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
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def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
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// peepholes
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def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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// brcond patterns
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// direct match equal/notequal zero branches
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def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
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(BNE CPURegs:$lhs, ZERO, bb:$dst)>;
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def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
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(BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
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def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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(BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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(BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
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(BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
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(BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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(BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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(BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
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(BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
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(BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
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def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
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(BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
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// generic brcond pattern
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def : Pat<(brcond CPURegs:$cond, bb:$dst),
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(BNE CPURegs:$cond, ZERO, bb:$dst)>;
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// setcc patterns, only matched when there
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// is no brcond following a setcc operation
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// select patterns
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def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
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def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
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def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
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def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
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def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
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(MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
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def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
|
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(MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
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||||
def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
|
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(MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
|
||||
|
||||
def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
|
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(MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
|
||||
|
||||
// setcc patterns
|
||||
def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
|
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(SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
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||||
def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
|
||||
|
||||
def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
|
||||
def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
|
||||
|
|
@ -637,18 +694,10 @@ def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
|
|||
def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
||||
|
||||
def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
|
||||
(OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLT CPURegs:$rhs, CPURegs:$lhs))>;
|
||||
|
||||
def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
|
||||
|
||||
def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
|
||||
def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
|
||||
(XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;
|
||||
def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Support
|
||||
|
|
|
|||
|
|
@ -58,6 +58,8 @@ MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
|
|||
HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
|
||||
HasSEInReg = true;
|
||||
HasBitCount = true;
|
||||
HasSwap = true;
|
||||
HasCondMov = true;
|
||||
}
|
||||
|
||||
// Abicall is the default for O32 ABI and is ignored
|
||||
|
|
|
|||
Loading…
Reference in New Issue