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[SystemZ] Support load-and-zero-rightmost-byte facility 

This adds support for the LZRF/LZRG/LLZRGF instructions that were
added on z13, and uses them for code generation were appropriate.

SystemZDAGToDAGISel::tryRISBGZero is updated again to prefer LLZRGF
over RISBG where both would be possible.

llvm-svn: 286586
This commit is contained in:
Ulrich Weigand 2016-11-11 12:46:28 +00:00
parent 5dc7b67c62
commit 92c2c672e5
10 changed files with 507 additions and 3 deletions
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6
llvm/lib/Target/SystemZ/SystemZFeatures.td
View File

@ -111,6 +111,11 @@ def Arch10NewFeatures : SystemZFeatureList<[
//
//===----------------------------------------------------------------------===//
def FeatureLoadAndZeroRightmostByte : SystemZFeature<
"load-and-zero-rightmost-byte", "LoadAndZeroRightmostByte",
"Assume that the load-and-zero-rightmost-byte facility is installed"
>;
def FeatureLoadStoreOnCond2 : SystemZFeature<
"load-store-on-cond-2", "LoadStoreOnCond2",
"Assume that the load/store-on-condition facility 2 is installed"
@ -123,6 +128,7 @@ def FeatureVector : SystemZFeature<
def FeatureNoVector : SystemZMissingFeature<"Vector">;
def Arch11NewFeatures : SystemZFeatureList<[
FeatureLoadAndZeroRightmostByte,
FeatureLoadStoreOnCond2,
FeatureVector
]>;

10
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -957,6 +957,16 @@ bool SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
SystemZ::isImmLF(~RISBG.Mask) ||
SystemZ::isImmHF(~RISBG.Mask))
PreferAnd = true;
// And likewise for the LLZRGF instruction, which doesn't have a register
// to register version.
else if (auto *Load = dyn_cast<LoadSDNode>(RISBG.Input)) {
if (Load->getMemoryVT() == MVT::i32 &&
(Load->getExtensionType() == ISD::EXTLOAD ||
Load->getExtensionType() == ISD::ZEXTLOAD) &&
RISBG.Mask == 0xffffff00 &&
Subtarget->hasLoadAndZeroRightmostByte())
PreferAnd = true;
}
if (PreferAnd) {
// Replace the current node with an AND. Note that the current node
// might already be that same AND, in which case it is already CSE'd

17
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -387,6 +387,16 @@ let canFoldAsLoad = 1 in {
def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
}
// Load and zero rightmost byte.
let Predicates = [FeatureLoadAndZeroRightmostByte] in {
def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>;
def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>;
def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00),
(LZRF bdxaddr20only:$src)>;
def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00),
(LZRG bdxaddr20only:$src)>;
}
// Register stores.
let SimpleBDXStore = 1 in {
// Expands to ST, STY or STFH, depending on the choice of register.
@ -583,6 +593,13 @@ def : Pat<(and GR64:$src, 0x7fffffff),
def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff),
(LLGT bdxaddr20only:$src)>;
// Load and zero rightmost byte.
let Predicates = [FeatureLoadAndZeroRightmostByte] in {
def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>;
def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00),
(LLZRGF bdxaddr20only:$src)>;
}
//===----------------------------------------------------------------------===//
// Truncations
//===----------------------------------------------------------------------===//

6
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
View File

@ -194,6 +194,9 @@ def : InstRW<[FXa], (instregex "LG(F|H)I$")>;
def : InstRW<[FXa], (instregex "LHI(Mux)?$")>;
def : InstRW<[FXa], (instregex "LR(Mux)?$")>;
// Load and zero rightmost byte
def : InstRW<[LSU], (instregex "LZR(F|G)$")>;
// Load and test
def : InstRW<[FXa, LSU, Lat5], (instregex "LT(G)?$")>;
def : InstRW<[FXa], (instregex "LT(G)?R$")>;
@ -244,6 +247,9 @@ def : InstRW<[FXa, LSU, Lat5], (instregex "LL(C|H)H$")>;
def : InstRW<[LSU], (instregex "LLHRL$")>;
def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
// Load and zero rightmost byte
def : InstRW<[LSU], (instregex "LLZRGF$")>;
//===----------------------------------------------------------------------===//
// Truncations
//===----------------------------------------------------------------------===//

7
llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
View File

@ -40,9 +40,10 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
HasPopulationCount(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
HasTransactionalExecution(false), HasProcessorAssist(false),
HasVector(false), HasLoadStoreOnCond2(false), TargetTriple(TT),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(), FrameLowering() {}
HasVector(false), HasLoadStoreOnCond2(false),
HasLoadAndZeroRightmostByte(false),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this), TSInfo(), FrameLowering() {}
bool SystemZSubtarget::isPC32DBLSymbol(const GlobalValue *GV,
CodeModel::Model CM) const {

6
llvm/lib/Target/SystemZ/SystemZSubtarget.h
View File

@ -46,6 +46,7 @@ protected:
bool HasProcessorAssist;
bool HasVector;
bool HasLoadStoreOnCond2;
bool HasLoadAndZeroRightmostByte;
private:
Triple TargetTriple;
@ -115,6 +116,11 @@ public:
// Return true if the target has the processor-assist facility.
bool hasProcessorAssist() const { return HasProcessorAssist; }
// Return true if the target has the load-and-zero-rightmost-byte facility.
bool hasLoadAndZeroRightmostByte() const {
return HasLoadAndZeroRightmostByte;
}
// Return true if the target has the vector facility.
bool hasVector() const { return HasVector; }

278
llvm/test/CodeGen/SystemZ/int-conv-13.ll Normal file
View File

@ -0,0 +1,278 @@
; Test load and zero rightmost byte.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; Check LZRF with no displacement.
define i32 @f1(i32 *%src) {
; CHECK-LABEL: f1:
; CHECK: lzrf %r2, 0(%r2)
; CHECK: br %r14
%val = load i32, i32 *%src
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the high end of the LZRF range.
define i32 @f2(i32 *%src) {
; CHECK-LABEL: f2:
; CHECK: lzrf %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131071
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f3(i32 *%src) {
; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lzrf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the high end of the negative LZRF range.
define i32 @f4(i32 *%src) {
; CHECK-LABEL: f4:
; CHECK: lzrf %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -1
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the low end of the LZRF range.
define i32 @f5(i32 *%src) {
; CHECK-LABEL: f5:
; CHECK: lzrf %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 *%src) {
; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524292
; CHECK: lzrf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131073
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check that LZRF allows an index.
define i32 @f7(i64 %src, i64 %index) {
; CHECK-LABEL: f7:
; CHECK: lzrf %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i32 *
%val = load i32 , i32 *%ptr
%and = and i32 %val, 4294967040
ret i32 %and
}
; Check LZRG with no displacement.
define i64 @f8(i64 *%src) {
; CHECK-LABEL: f8:
; CHECK: lzrg %r2, 0(%r2)
; CHECK: br %r14
%val = load i64, i64 *%src
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the high end of the LZRG range.
define i64 @f9(i64 *%src) {
; CHECK-LABEL: f9:
; CHECK: lzrg %r2, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 65535
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f10(i64 *%src) {
; CHECK-LABEL: f10:
; CHECK: agfi %r2, 524288
; CHECK: lzrg %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 65536
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the high end of the negative LZRG range.
define i64 @f11(i64 *%src) {
; CHECK-LABEL: f11:
; CHECK: lzrg %r2, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 -1
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the low end of the LZRG range.
define i64 @f12(i64 *%src) {
; CHECK-LABEL: f12:
; CHECK: lzrg %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 -65536
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f13(i64 *%src) {
; CHECK-LABEL: f13:
; CHECK: agfi %r2, -524296
; CHECK: lzrg %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 -65537
%val = load i64, i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check that LZRG allows an index.
define i64 @f14(i64 %src, i64 %index) {
; CHECK-LABEL: f14:
; CHECK: lzrg %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i64 *
%val = load i64 , i64 *%ptr
%and = and i64 %val, 18446744073709551360
ret i64 %and
}
; Check LLZRGF with no displacement.
define i64 @f15(i32 *%src) {
; CHECK-LABEL: f15:
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%val = load i32, i32 *%src
%ext = zext i32 %val to i64
%and = and i64 %ext, 18446744073709551360
ret i64 %and
}
; ... and the other way around.
define i64 @f16(i32 *%src) {
; CHECK-LABEL: f16:
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%val = load i32, i32 *%src
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the high end of the LLZRGF range.
define i64 @f17(i32 *%src) {
; CHECK-LABEL: f17:
; CHECK: llzrgf %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131071
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f18(i32 *%src) {
; CHECK-LABEL: f18:
; CHECK: agfi %r2, 524288
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the high end of the negative LLZRGF range.
define i64 @f19(i32 *%src) {
; CHECK-LABEL: f19:
; CHECK: llzrgf %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -1
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the low end of the LLZRGF range.
define i64 @f20(i32 *%src) {
; CHECK-LABEL: f20:
; CHECK: llzrgf %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131072
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f21(i32 *%src) {
; CHECK-LABEL: f21:
; CHECK: agfi %r2, -524292
; CHECK: llzrgf %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 -131073
%val = load i32, i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check that LLZRGF allows an index.
define i64 @f22(i64 %src, i64 %index) {
; CHECK-LABEL: f22:
; CHECK: llzrgf %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i32 *
%val = load i32 , i32 *%ptr
%and = and i32 %val, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}
; Check that we still get a RISBGN if the source is in a register.
define i64 @f23(i32 %src) {
; CHECK-LABEL: f23:
; CHECK: risbgn %r2, %r2, 32, 183, 0
; CHECK: br %r14
%and = and i32 %src, 4294967040
%ext = zext i32 %and to i64
ret i64 %ext
}

90
llvm/test/MC/Disassembler/SystemZ/insns-z13.txt
View File

@ -2,6 +2,96 @@
# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z13 \
# RUN: | FileCheck %s
# CHECK: lzrf %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x3b
# CHECK: lzrf %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0x3b
# CHECK: lzrf %r0, 0
0xe3 0x00 0x00 0x00 0x00 0x3b
# CHECK: lzrf %r0, 1
0xe3 0x00 0x00 0x01 0x00 0x3b
# CHECK: lzrf %r0, 524287
0xe3 0x00 0x0f 0xff 0x7f 0x3b
# CHECK: lzrf %r0, 0(%r1)
0xe3 0x00 0x10 0x00 0x00 0x3b
# CHECK: lzrf %r0, 0(%r15)
0xe3 0x00 0xf0 0x00 0x00 0x3b
# CHECK: lzrf %r0, 524287(%r1,%r15)
0xe3 0x01 0xff 0xff 0x7f 0x3b
# CHECK: lzrf %r0, 524287(%r15,%r1)
0xe3 0x0f 0x1f 0xff 0x7f 0x3b
# CHECK: lzrf %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x3b
# CHECK: lzrg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x2a
# CHECK: lzrg %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0x2a
# CHECK: lzrg %r0, 0
0xe3 0x00 0x00 0x00 0x00 0x2a
# CHECK: lzrg %r0, 1
0xe3 0x00 0x00 0x01 0x00 0x2a
# CHECK: lzrg %r0, 524287
0xe3 0x00 0x0f 0xff 0x7f 0x2a
# CHECK: lzrg %r0, 0(%r1)
0xe3 0x00 0x10 0x00 0x00 0x2a
# CHECK: lzrg %r0, 0(%r15)
0xe3 0x00 0xf0 0x00 0x00 0x2a
# CHECK: lzrg %r0, 524287(%r1,%r15)
0xe3 0x01 0xff 0xff 0x7f 0x2a
# CHECK: lzrg %r0, 524287(%r15,%r1)
0xe3 0x0f 0x1f 0xff 0x7f 0x2a
# CHECK: lzrg %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x2a
# CHECK: llzrgf %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x3a
# CHECK: llzrgf %r0, -1
0xe3 0x00 0x0f 0xff 0xff 0x3a
# CHECK: llzrgf %r0, 0
0xe3 0x00 0x00 0x00 0x00 0x3a
# CHECK: llzrgf %r0, 1
0xe3 0x00 0x00 0x01 0x00 0x3a
# CHECK: llzrgf %r0, 524287
0xe3 0x00 0x0f 0xff 0x7f 0x3a
# CHECK: llzrgf %r0, 0(%r1)
0xe3 0x00 0x10 0x00 0x00 0x3a
# CHECK: llzrgf %r0, 0(%r15)
0xe3 0x00 0xf0 0x00 0x00 0x3a
# CHECK: llzrgf %r0, 524287(%r1,%r15)
0xe3 0x01 0xff 0xff 0x7f 0x3a
# CHECK: llzrgf %r0, 524287(%r15,%r1)
0xe3 0x0f 0x1f 0xff 0x7f 0x3a
# CHECK: llzrgf %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x3a
#CHECK: lcbb %r0, 0, 0
0xe7 0x00 0x00 0x00 0x00 0x27

24
llvm/test/MC/SystemZ/insn-bad-z13.s
View File

@ -4,6 +4,30 @@
# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch11 < %s 2> %t
# RUN: FileCheck < %t %s
#CHECK: error: invalid operand
#CHECK: lzrf %r0, -524289
#CHECK: error: invalid operand
#CHECK: lzrf %r0, 524288
lzrf %r0, -524289
lzrf %r0, 524288
#CHECK: error: invalid operand
#CHECK: lzrg %r0, -524289
#CHECK: error: invalid operand
#CHECK: lzrg %r0, 524288
lzrg %r0, -524289
lzrg %r0, 524288
#CHECK: error: invalid operand
#CHECK: llzrgf %r0, -524289
#CHECK: error: invalid operand
#CHECK: llzrgf %r0, 524288
llzrgf %r0, -524289
llzrgf %r0, 524288
#CHECK: error: invalid operand
#CHECK: lcbb %r0, 0, -1
#CHECK: error: invalid operand

66
llvm/test/MC/SystemZ/insn-good-z13.s
View File

@ -4,6 +4,72 @@
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch11 -show-encoding %s \
# RUN: | FileCheck %s
#CHECK: lzrf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x3b]
#CHECK: lzrf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x3b]
#CHECK: lzrf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x3b]
#CHECK: lzrf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x3b]
#CHECK: lzrf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x3b]
#CHECK: lzrf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x3b]
#CHECK: lzrf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x3b]
#CHECK: lzrf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x3b]
#CHECK: lzrf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x3b]
#CHECK: lzrf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x3b]
lzrf %r0, -524288
lzrf %r0, -1
lzrf %r0, 0
lzrf %r0, 1
lzrf %r0, 524287
lzrf %r0, 0(%r1)
lzrf %r0, 0(%r15)
lzrf %r0, 524287(%r1,%r15)
lzrf %r0, 524287(%r15,%r1)
lzrf %r15, 0
#CHECK: lzrg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x2a]
#CHECK: lzrg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x2a]
#CHECK: lzrg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x2a]
#CHECK: lzrg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x2a]
#CHECK: lzrg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x2a]
#CHECK: lzrg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x2a]
#CHECK: lzrg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x2a]
#CHECK: lzrg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x2a]
#CHECK: lzrg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x2a]
#CHECK: lzrg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x2a]
lzrg %r0, -524288
lzrg %r0, -1
lzrg %r0, 0
lzrg %r0, 1
lzrg %r0, 524287
lzrg %r0, 0(%r1)
lzrg %r0, 0(%r15)
lzrg %r0, 524287(%r1,%r15)
lzrg %r0, 524287(%r15,%r1)
lzrg %r15, 0
#CHECK: llzrgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x3a]
#CHECK: llzrgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x3a]
#CHECK: llzrgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x3a]
#CHECK: llzrgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x3a]
#CHECK: llzrgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x3a]
#CHECK: llzrgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x3a]
#CHECK: llzrgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x3a]
#CHECK: llzrgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x3a]
#CHECK: llzrgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x3a]
#CHECK: llzrgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x3a]
llzrgf %r0, -524288
llzrgf %r0, -1
llzrgf %r0, 0
llzrgf %r0, 1
llzrgf %r0, 524287
llzrgf %r0, 0(%r1)
llzrgf %r0, 0(%r15)
llzrgf %r0, 524287(%r1,%r15)
llzrgf %r0, 524287(%r15,%r1)
llzrgf %r15, 0
#CHECK: lcbb %r0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x27]
#CHECK: lcbb %r0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x27]
#CHECK: lcbb %r0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x27]