forked from OSchip/llvm-project
[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cpp
Making sure that an instruction has fewer operands than required, then attempting to access one out of range is going to fail. llvm-svn: 316785
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@ -1759,7 +1759,7 @@ bool HCE::replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI) {
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// Update offsets of the def's uses.
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for (std::pair<MachineInstr*,unsigned> P : RegOps) {
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unsigned J = P.second;
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assert(P.first->getNumOperands() < J+1 &&
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assert(P.first->getNumOperands() > J+1 &&
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P.first->getOperand(J+1).isImm());
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MachineOperand &ImmOp = P.first->getOperand(J+1);
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ImmOp.setImm(ImmOp.getImm() + Diff);
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@ -0,0 +1,45 @@
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# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s
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# An incorrect assertion was triggered on this code, while attempting to
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# perform a valid transformation.
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# CHECK: PS_jmpret
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--- |
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define void @fred() { ret void }
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@array = global [1024 x i8] zeroinitializer, align 8
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...
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---
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name: fred
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tracksRegLiveness: true
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: intregs }
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- { id: 2, class: intregs }
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- { id: 3, class: predregs }
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- { id: 4, class: intregs }
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- { id: 5, class: intregs }
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- { id: 6, class: intregs }
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- { id: 7, class: intregs }
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- { id: 8, class: intregs }
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- { id: 9, class: intregs }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0 = COPY %r1
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%1 = COPY %r0
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%2 = A2_tfrsi @array
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%3 = IMPLICIT_DEF
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%4 = A2_tfrsi @array+424
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%5 = M2_macsip %0, %1, 5
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%6 = A2_addi %2, 704
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%7 = A2_tfrsi 0
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S4_pstorerif_rr %3, %6, %5, 2, %7
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%8 = A2_tfrsi @array+144
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%9 = C2_mux %3, %4, %8
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S4_storeiri_io %9, 0, 0
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PS_jmpret %r31, implicit-def %pc
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...
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