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[X86][SSE] Add computeKnownBitsForTargetNode support for (V)PSLL/(V)PSRL instructions 

llvm-svn: 298806
This commit is contained in:
Simon Pilgrim 2017-03-26 13:17:55 +00:00
parent 049d9c921f
commit 92925ea701
2 changed files with 26 additions and 2 deletions
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27
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -26591,6 +26591,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
unsigned Depth) const { unsigned Depth) const {
unsigned BitWidth = KnownZero.getBitWidth(); unsigned BitWidth = KnownZero.getBitWidth();
unsigned Opc = Op.getOpcode(); unsigned Opc = Op.getOpcode();
EVT VT = Op.getValueType();
assert((Opc >= ISD::BUILTIN_OP_END || assert((Opc >= ISD::BUILTIN_OP_END ||
Opc == ISD::INTRINSIC_WO_CHAIN || Opc == ISD::INTRINSIC_WO_CHAIN ||
Opc == ISD::INTRINSIC_W_CHAIN || Opc == ISD::INTRINSIC_W_CHAIN ||
@ -26624,9 +26625,33 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
KnownZero.setBits(NumLoBits, BitWidth); KnownZero.setBits(NumLoBits, BitWidth);
break; break;
} }
case X86ISD::VSHLI:
case X86ISD::VSRLI: {
if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
if (ShiftImm->getAPIntValue().uge(VT.getScalarSizeInBits())) {
KnownZero = APInt::getAllOnesValue(BitWidth);
break;
}
DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
unsigned ShAmt = ShiftImm->getZExtValue();
if (Opc == X86ISD::VSHLI) {
KnownZero = KnownZero << ShAmt;
KnownOne = KnownOne << ShAmt;
// Low bits are known zero.
KnownZero.setLowBits(ShAmt);
} else {
KnownZero = KnownZero.lshr(ShAmt);
KnownOne = KnownOne.lshr(ShAmt);
// High bits are known zero.
KnownZero.setHighBits(ShAmt);
}
}
break;
}
case X86ISD::VZEXT: { case X86ISD::VZEXT: {
SDValue N0 = Op.getOperand(0); SDValue N0 = Op.getOperand(0);
unsigned NumElts = Op.getValueType().getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
EVT SrcVT = N0.getValueType(); EVT SrcVT = N0.getValueType();
unsigned InNumElts = SrcVT.getVectorNumElements(); unsigned InNumElts = SrcVT.getVectorNumElements();

1
llvm/test/CodeGen/X86/combine-abs.ll
View File

@ -84,7 +84,6 @@ define <8 x i32> @combine_v8i32_abs_pos(<8 x i32> %a) {
; CHECK-LABEL: combine_v8i32_abs_pos: ; CHECK-LABEL: combine_v8i32_abs_pos:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0 ; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
; CHECK-NEXT: vpabsd %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = lshr <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %1 = lshr <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %1) %2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %1)