forked from OSchip/llvm-project
[ARM,MVE] Add intrinsics for the VQDMLAH family.
Summary: These are complicated integer multiply+add instructions with extra saturation, taking the high half of a double-width product, and optional rounding. There's no sensible way to represent that in standard IR, so I've converted the clang builtins directly to target-specific intrinsics. Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard Reviewed By: miyuki Subscribers: kristof.beyls, hiraditya, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D76123
This commit is contained in:
Simon Tatham
parent
28c5d97bee
commit
928776de92
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@ -220,6 +220,29 @@ let params = T.Int, pnt = PNT_NType in {
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$m1, $m2, $addend_s, $pred)>;
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}
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multiclass VQDMLA {
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def hq_n: Intrinsic<
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Vector, (args Vector:$addend, Vector:$m1, Scalar:$m2_s),
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(IRInt<NAME # "h", [Vector]> $addend, $m1, $m2_s)>;
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def shq_n: Intrinsic<
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Vector, (args Vector:$m1, Vector:$m2, Scalar:$addend_s),
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(IRInt<NAME # "sh", [Vector]> $m1, $m2, $addend_s)>;
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def hq_m_n: Intrinsic<
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Vector, (args Vector:$addend, Vector:$m1, Scalar:$m2_s, Predicate:$pred),
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(IRInt<NAME # "h_predicated", [Vector, Predicate]>
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$addend, $m1, $m2_s, $pred)>;
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def shq_m_n: Intrinsic<
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Vector, (args Vector:$m1, Vector:$m2, Scalar:$addend_s, Predicate:$pred),
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(IRInt<NAME # "sh_predicated", [Vector, Predicate]>
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$m1, $m2, $addend_s, $pred)>;
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}
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let params = T.Signed, pnt = PNT_NType in {
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defm vqdmla: VQDMLA;
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defm vqrdmla: VQDMLA;
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}
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let params = !listconcat(T.Int16, T.Int32) in {
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let pnt = PNT_None in {
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def vmvnq_n: Intrinsic<Vector, (args imm_simd_vmvn:$imm),
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@ -316,6 +316,129 @@ uint32x4_t test_vmlasq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c) {
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqdmlahq_n_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]])
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// CHECK-NEXT: ret <16 x i8> [[TMP1]]
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//
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int8x16_t test_vqdmlahq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
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#ifdef POLYMORPHIC
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return vqdmlahq(a, b, c);
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#else /* POLYMORPHIC */
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return vqdmlahq_n_s8(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqdmlahq_n_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]])
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// CHECK-NEXT: ret <8 x i16> [[TMP1]]
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//
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int16x8_t test_vqdmlahq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
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#ifdef POLYMORPHIC
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return vqdmlahq(a, b, c);
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#else /* POLYMORPHIC */
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return vqdmlahq_n_s16(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqdmlahq_n_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]])
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// CHECK-NEXT: ret <4 x i32> [[TMP0]]
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//
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int32x4_t test_vqdmlahq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
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#ifdef POLYMORPHIC
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return vqdmlahq(a, b, c);
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#else /* POLYMORPHIC */
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return vqdmlahq_n_s32(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlahq_n_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]])
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// CHECK-NEXT: ret <16 x i8> [[TMP1]]
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//
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int8x16_t test_vqrdmlahq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
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#ifdef POLYMORPHIC
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return vqrdmlahq(a, b, c);
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#else /* POLYMORPHIC */
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return vqrdmlahq_n_s8(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlahq_n_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]])
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// CHECK-NEXT: ret <8 x i16> [[TMP1]]
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//
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int16x8_t test_vqrdmlahq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
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#ifdef POLYMORPHIC
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return vqrdmlahq(a, b, c);
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#else /* POLYMORPHIC */
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return vqrdmlahq_n_s16(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlahq_n_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]])
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// CHECK-NEXT: ret <4 x i32> [[TMP0]]
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//
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int32x4_t test_vqrdmlahq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
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#ifdef POLYMORPHIC
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return vqrdmlahq(a, b, c);
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#else /* POLYMORPHIC */
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return vqrdmlahq_n_s32(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlashq_n_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 [[TMP0]])
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// CHECK-NEXT: ret <16 x i8> [[TMP1]]
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//
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int8x16_t test_vqrdmlashq_n_s8(int8x16_t a, int8x16_t b, int8_t c) {
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#ifdef POLYMORPHIC
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return vqrdmlashq(a, b, c);
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#else /* POLYMORPHIC */
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return vqrdmlashq_n_s8(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlashq_n_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 [[TMP0]])
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// CHECK-NEXT: ret <8 x i16> [[TMP1]]
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//
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int16x8_t test_vqrdmlashq_n_s16(int16x8_t a, int16x8_t b, int16_t c) {
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#ifdef POLYMORPHIC
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return vqrdmlashq(a, b, c);
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#else /* POLYMORPHIC */
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return vqrdmlashq_n_s16(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlashq_n_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[C:%.*]])
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// CHECK-NEXT: ret <4 x i32> [[TMP0]]
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//
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int32x4_t test_vqrdmlashq_n_s32(int32x4_t a, int32x4_t b, int32_t c) {
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#ifdef POLYMORPHIC
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return vqrdmlashq(a, b, c);
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#else /* POLYMORPHIC */
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return vqrdmlashq_n_s32(a, b, c);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vfmaq_m_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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@ -639,3 +762,145 @@ uint32x4_t test_vmlasq_m_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c, mve_pred1
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return vmlasq_m_n_u32(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqdmlahq_m_n_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
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// CHECK-NEXT: ret <16 x i8> [[TMP3]]
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//
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int8x16_t test_vqdmlahq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vqdmlahq_m(a, b, c, p);
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#else /* POLYMORPHIC */
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return vqdmlahq_m_n_s8(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqdmlahq_m_n_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
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// CHECK-NEXT: ret <8 x i16> [[TMP3]]
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//
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int16x8_t test_vqdmlahq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vqdmlahq_m(a, b, c, p);
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#else /* POLYMORPHIC */
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return vqdmlahq_m_n_s16(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqdmlahq_m_n_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
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// CHECK-NEXT: ret <4 x i32> [[TMP2]]
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//
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int32x4_t test_vqdmlahq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vqdmlahq_m(a, b, c, p);
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#else /* POLYMORPHIC */
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return vqdmlahq_m_n_s32(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlahq_m_n_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8> [[B:%.*]], <16 x i8> [[A:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
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// CHECK-NEXT: ret <16 x i8> [[TMP3]]
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//
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int8x16_t test_vqrdmlahq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vqrdmlahq_m(a, b, c, p);
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#else /* POLYMORPHIC */
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return vqrdmlahq_m_n_s8(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlahq_m_n_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16> [[B:%.*]], <8 x i16> [[A:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
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// CHECK-NEXT: ret <8 x i16> [[TMP3]]
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//
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int16x8_t test_vqrdmlahq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vqrdmlahq_m(a, b, c, p);
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#else /* POLYMORPHIC */
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return vqrdmlahq_m_n_s16(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlahq_m_n_s32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32> [[B:%.*]], <4 x i32> [[A:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
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// CHECK-NEXT: ret <4 x i32> [[TMP2]]
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//
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int32x4_t test_vqrdmlahq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vqrdmlahq_m(a, b, c, p);
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#else /* POLYMORPHIC */
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return vqrdmlahq_m_n_s32(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlashq_m_n_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 [[TMP0]], <16 x i1> [[TMP2]])
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// CHECK-NEXT: ret <16 x i8> [[TMP3]]
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//
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int8x16_t test_vqrdmlashq_m_n_s8(int8x16_t a, int8x16_t b, int8_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vqrdmlashq_m(a, b, c, p);
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#else /* POLYMORPHIC */
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return vqrdmlashq_m_n_s8(a, b, c, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vqrdmlashq_m_n_s16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[C:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP1]])
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// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 [[TMP0]], <8 x i1> [[TMP2]])
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// CHECK-NEXT: ret <8 x i16> [[TMP3]]
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//
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int16x8_t test_vqrdmlashq_m_n_s16(int16x8_t a, int16x8_t b, int16_t c, mve_pred16_t p) {
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#ifdef POLYMORPHIC
|
||||
return vqrdmlashq_m(a, b, c, p);
|
||||
#else /* POLYMORPHIC */
|
||||
return vqrdmlashq_m_n_s16(a, b, c, p);
|
||||
#endif /* POLYMORPHIC */
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vqrdmlashq_m_n_s32(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[C:%.*]], <4 x i1> [[TMP1]])
|
||||
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
|
||||
//
|
||||
int32x4_t test_vqrdmlashq_m_n_s32(int32x4_t a, int32x4_t b, int32_t c, mve_pred16_t p) {
|
||||
#ifdef POLYMORPHIC
|
||||
return vqrdmlashq_m(a, b, c, p);
|
||||
#else /* POLYMORPHIC */
|
||||
return vqrdmlashq_m_n_s32(a, b, c, p);
|
||||
#endif /* POLYMORPHIC */
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1255,6 +1255,19 @@ def int_arm_mve_vmlas_n_predicated: Intrinsic<[llvm_anyvector_ty],
|
|||
llvm_i32_ty /* addend (scalar) */, llvm_anyvector_ty /* pred */],
|
||||
[IntrNoMem]>;
|
||||
|
||||
defm int_arm_mve_vqdmlah: MVEPredicated<[llvm_anyvector_ty],
|
||||
[LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
|
||||
llvm_i32_ty /* mult op #2 (scalar) */]>;
|
||||
defm int_arm_mve_vqrdmlah: MVEPredicated<[llvm_anyvector_ty],
|
||||
[LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
|
||||
llvm_i32_ty /* mult op #2 (scalar) */]>;
|
||||
defm int_arm_mve_vqdmlash: MVEPredicated<[llvm_anyvector_ty],
|
||||
[LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
|
||||
llvm_i32_ty /* addend (scalar) */]>;
|
||||
defm int_arm_mve_vqrdmlash: MVEPredicated<[llvm_anyvector_ty],
|
||||
[LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
|
||||
llvm_i32_ty /* addend (scalar) */]>;
|
||||
|
||||
// CDE (Custom Datapath Extension)
|
||||
|
||||
def int_arm_cde_cx1: Intrinsic<
|
||||
|
|
|
|||
|
|
@ -14325,8 +14325,16 @@ SDValue ARMTargetLowering::PerformIntrinsicCombine(SDNode *N,
|
|||
// No immediate versions of these to check for.
|
||||
break;
|
||||
|
||||
case Intrinsic::arm_mve_vqdmlah:
|
||||
case Intrinsic::arm_mve_vqdmlash:
|
||||
case Intrinsic::arm_mve_vqrdmlah:
|
||||
case Intrinsic::arm_mve_vqrdmlash:
|
||||
case Intrinsic::arm_mve_vmla_n_predicated:
|
||||
case Intrinsic::arm_mve_vmlas_n_predicated: {
|
||||
case Intrinsic::arm_mve_vmlas_n_predicated:
|
||||
case Intrinsic::arm_mve_vqdmlah_predicated:
|
||||
case Intrinsic::arm_mve_vqdmlash_predicated:
|
||||
case Intrinsic::arm_mve_vqrdmlah_predicated:
|
||||
case Intrinsic::arm_mve_vqrdmlash_predicated: {
|
||||
// These intrinsics all take an i32 scalar operand which is narrowed to the
|
||||
// size of a single lane of the vector type they return. So we don't need
|
||||
// any bits of that operand above that point, which allows us to eliminate
|
||||
|
|
|
|||
|
|
@ -5242,10 +5242,30 @@ class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
|
|||
let Inst{5} = bit_5;
|
||||
}
|
||||
|
||||
multiclass MVE_VQDMLAH_qr_multi<string iname, MVEVectorVTInfo VTI,
|
||||
bit bit_5, bit bit_12> {
|
||||
def "": MVE_VQDMLAH_qr<iname, VTI.Suffix, 0b0, VTI.Size, bit_5, bit_12>;
|
||||
defvar Inst = !cast<Instruction>(NAME);
|
||||
defvar unpred_int = !cast<Intrinsic>("int_arm_mve_" # iname);
|
||||
defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # iname # "_predicated");
|
||||
|
||||
let Predicates = [HasMVEInt] in {
|
||||
def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
|
||||
(i32 rGPR:$s))),
|
||||
(VTI.Vec (Inst (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
|
||||
(i32 rGPR:$s)))>;
|
||||
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
|
||||
(i32 rGPR:$s), (VTI.Pred VCCR:$pred))),
|
||||
(VTI.Vec (Inst (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
|
||||
(i32 rGPR:$s), ARMVCCThen,
|
||||
(VTI.Pred VCCR:$pred)))>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
|
||||
def s8 : MVE_VQDMLAH_qr<iname, "s8", 0b0, 0b00, bit_5, bit_12>;
|
||||
def s16 : MVE_VQDMLAH_qr<iname, "s16", 0b0, 0b01, bit_5, bit_12>;
|
||||
def s32 : MVE_VQDMLAH_qr<iname, "s32", 0b0, 0b10, bit_5, bit_12>;
|
||||
defm s8 : MVE_VQDMLAH_qr_multi<iname, MVE_v16s8, bit_5, bit_12>;
|
||||
defm s16 : MVE_VQDMLAH_qr_multi<iname, MVE_v8s16, bit_5, bit_12>;
|
||||
defm s32 : MVE_VQDMLAH_qr_multi<iname, MVE_v4s32, bit_5, bit_12>;
|
||||
}
|
||||
|
||||
defm MVE_VQDMLAH_qr : MVE_VQDMLAH_qr_types<"vqdmlah", 0b1, 0b0>;
|
||||
|
|
|
|||
|
|
@ -263,6 +263,102 @@ entry:
|
|||
ret <4 x i32> %1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @test_vqdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
|
||||
; CHECK-LABEL: test_vqdmlahq_n_s8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqdmlah.s8 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i8 %c to i32
|
||||
%1 = tail call <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)
|
||||
ret <16 x i8> %1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @test_vqdmlahq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
|
||||
; CHECK-LABEL: test_vqdmlahq_n_s16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqdmlah.s16 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %c to i32
|
||||
%1 = tail call <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)
|
||||
ret <8 x i16> %1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @test_vqdmlahq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
|
||||
; CHECK-LABEL: test_vqdmlahq_n_s32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqdmlah.s32 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = tail call <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
|
||||
; CHECK-LABEL: test_vqrdmlahq_n_s8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqrdmlah.s8 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i8 %c to i32
|
||||
%1 = tail call <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)
|
||||
ret <16 x i8> %1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
|
||||
; CHECK-LABEL: test_vqrdmlahq_n_s16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqrdmlah.s16 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %c to i32
|
||||
%1 = tail call <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)
|
||||
ret <8 x i16> %1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
|
||||
; CHECK-LABEL: test_vqrdmlahq_n_s32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqrdmlah.s32 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = tail call <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlashq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
|
||||
; CHECK-LABEL: test_vqrdmlashq_n_s8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqrdmlash.s8 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i8 %c to i32
|
||||
%1 = tail call <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8> %a, <16 x i8> %b, i32 %0)
|
||||
ret <16 x i8> %1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlashq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
|
||||
; CHECK-LABEL: test_vqrdmlashq_n_s16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqrdmlash.s16 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %c to i32
|
||||
%1 = tail call <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16> %a, <8 x i16> %b, i32 %0)
|
||||
ret <8 x i16> %1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlashq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
|
||||
; CHECK-LABEL: test_vqrdmlashq_n_s32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vqrdmlash.s32 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = tail call <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32> %a, <4 x i32> %b, i32 %c)
|
||||
ret <4 x i32> %0
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x half> @test_vfmaq_m_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vfmaq_m_f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
|
|
@ -571,6 +667,138 @@ entry:
|
|||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @test_vqdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqdmlahq_m_n_s8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqdmlaht.s8 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i8 %c to i32
|
||||
%1 = zext i16 %p to i32
|
||||
%2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
|
||||
%3 = tail call <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
|
||||
ret <16 x i8> %3
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @test_vqdmlahq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqdmlahq_m_n_s16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqdmlaht.s16 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %c to i32
|
||||
%1 = zext i16 %p to i32
|
||||
%2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
|
||||
%3 = tail call <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
|
||||
ret <8 x i16> %3
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @test_vqdmlahq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqdmlahq_m_n_s32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqdmlaht.s32 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = tail call <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlahq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqrdmlahq_m_n_s8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqrdmlaht.s8 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i8 %c to i32
|
||||
%1 = zext i16 %p to i32
|
||||
%2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
|
||||
%3 = tail call <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
|
||||
ret <16 x i8> %3
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlahq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqrdmlahq_m_n_s16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqrdmlaht.s16 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %c to i32
|
||||
%1 = zext i16 %p to i32
|
||||
%2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
|
||||
%3 = tail call <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
|
||||
ret <8 x i16> %3
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlahq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqrdmlahq_m_n_s32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqrdmlaht.s32 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = tail call <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @test_vqrdmlashq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqrdmlashq_m_n_s8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqrdmlasht.s8 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i8 %c to i32
|
||||
%1 = zext i16 %p to i32
|
||||
%2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
|
||||
%3 = tail call <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
|
||||
ret <16 x i8> %3
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <8 x i16> @test_vqrdmlashq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqrdmlashq_m_n_s16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqrdmlasht.s16 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %c to i32
|
||||
%1 = zext i16 %p to i32
|
||||
%2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
|
||||
%3 = tail call <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
|
||||
ret <8 x i16> %3
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @test_vqrdmlashq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqrdmlashq_m_n_s32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqrdmlasht.s32 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = tail call <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
|
||||
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
|
||||
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
|
||||
|
|
@ -585,3 +813,21 @@ declare <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32>, <4 x i32
|
|||
declare <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
|
||||
declare <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
|
||||
declare <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
|
||||
declare <16 x i8> @llvm.arm.mve.vqdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
|
||||
declare <8 x i16> @llvm.arm.mve.vqdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
|
||||
declare <4 x i32> @llvm.arm.mve.vqdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
|
||||
declare <16 x i8> @llvm.arm.mve.vqrdmlah.v16i8(<16 x i8>, <16 x i8>, i32)
|
||||
declare <8 x i16> @llvm.arm.mve.vqrdmlah.v8i16(<8 x i16>, <8 x i16>, i32)
|
||||
declare <4 x i32> @llvm.arm.mve.vqrdmlah.v4i32(<4 x i32>, <4 x i32>, i32)
|
||||
declare <16 x i8> @llvm.arm.mve.vqrdmlash.v16i8(<16 x i8>, <16 x i8>, i32)
|
||||
declare <8 x i16> @llvm.arm.mve.vqrdmlash.v8i16(<8 x i16>, <8 x i16>, i32)
|
||||
declare <4 x i32> @llvm.arm.mve.vqrdmlash.v4i32(<4 x i32>, <4 x i32>, i32)
|
||||
declare <16 x i8> @llvm.arm.mve.vqdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
|
||||
declare <8 x i16> @llvm.arm.mve.vqdmlah.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
|
||||
declare <4 x i32> @llvm.arm.mve.vqdmlah.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
|
||||
declare <16 x i8> @llvm.arm.mve.vqrdmlah.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
|
||||
declare <8 x i16> @llvm.arm.mve.vqrdmlah.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
|
||||
declare <4 x i32> @llvm.arm.mve.vqrdmlah.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
|
||||
declare <16 x i8> @llvm.arm.mve.vqrdmlash.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
|
||||
declare <8 x i16> @llvm.arm.mve.vqrdmlash.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
|
||||
declare <4 x i32> @llvm.arm.mve.vqrdmlash.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>)
|
||||
|
|
|
|||
Loading…
Reference in New Issue