forked from OSchip/llvm-project
[SVE] Lower fixed length vXi32/vXi64 SDIV to scalable vectors.
Differential Revision: https://reviews.llvm.org/D85982
This commit is contained in:
Cameron McInally
parent
416a6a85b1
commit
92593f9e77
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@ -997,6 +997,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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// These operations are not supported on NEON but SVE can do them.
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setOperationAction(ISD::MUL, MVT::v1i64, Custom);
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setOperationAction(ISD::MUL, MVT::v2i64, Custom);
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setOperationAction(ISD::SDIV, MVT::v2i32, Custom);
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setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
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setOperationAction(ISD::SDIV, MVT::v1i64, Custom);
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setOperationAction(ISD::SDIV, MVT::v2i64, Custom);
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setOperationAction(ISD::SMAX, MVT::v1i64, Custom);
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setOperationAction(ISD::SMAX, MVT::v2i64, Custom);
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setOperationAction(ISD::SMIN, MVT::v1i64, Custom);
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@ -1129,6 +1133,10 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
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setOperationAction(ISD::UMIN, VT, Custom);
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setOperationAction(ISD::XOR, VT, Custom);
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setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
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if (VT.getVectorElementType() == MVT::i32 ||
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VT.getVectorElementType() == MVT::i64)
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setOperationAction(ISD::SDIV, VT, Custom);
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}
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void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
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@ -8925,6 +8933,12 @@ SDValue AArch64TargetLowering::LowerDIV(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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bool Signed = Op.getOpcode() == ISD::SDIV;
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unsigned PredOpcode = Signed ? AArch64ISD::SDIV_PRED : AArch64ISD::UDIV_PRED;
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if (useSVEForFixedLengthVectorVT(Op.getValueType(), /*OverrideNEON=*/true) &&
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(VT.getVectorElementType() == MVT::i32 ||
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VT.getVectorElementType() == MVT::i64))
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return LowerToPredicatedOp(Op, DAG, PredOpcode, /*OverrideNEON=*/true);
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if (VT == MVT::nxv4i32 || VT == MVT::nxv2i64)
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return LowerToPredicatedOp(Op, DAG, PredOpcode);
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@ -419,6 +419,170 @@ define void @add_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
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; VBYTES because the add tests already validate the legalisation code paths.
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;
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;
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; SDIV
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;
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; Vector v2i32 sdiv are not legal for NEON so use SVE when available.
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define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
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; CHECK-LABEL: sdiv_v2i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),2)]]
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; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
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; CHECK: ret
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%res = sdiv <2 x i32> %op1, %op2
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ret <2 x i32> %res
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}
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; Vector v4i32 sdiv are not legal for NEON so use SVE when available.
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define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
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; CHECK-LABEL: sdiv_v4i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),4)]]
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; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
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; CHECK: ret
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%res = sdiv <4 x i32> %op1, %op2
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ret <4 x i32> %res
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}
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define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
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; CHECK-LABEL: sdiv_v8i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
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; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
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; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <8 x i32>, <8 x i32>* %a
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%op2 = load <8 x i32>, <8 x i32>* %b
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%res = sdiv <8 x i32> %op1, %op2
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store <8 x i32> %res, <8 x i32>* %a
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ret void
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}
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define void @sdiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
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; CHECK-LABEL: sdiv_v16i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
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; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
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; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%op2 = load <16 x i32>, <16 x i32>* %b
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%res = sdiv <16 x i32> %op1, %op2
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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define void @sdiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
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; CHECK-LABEL: sdiv_v32i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
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; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
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; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <32 x i32>, <32 x i32>* %a
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%op2 = load <32 x i32>, <32 x i32>* %b
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%res = sdiv <32 x i32> %op1, %op2
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store <32 x i32> %res, <32 x i32>* %a
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ret void
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}
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define void @sdiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
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; CHECK-LABEL: sdiv_v64i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
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; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
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; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <64 x i32>, <64 x i32>* %a
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%op2 = load <64 x i32>, <64 x i32>* %b
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%res = sdiv <64 x i32> %op1, %op2
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store <64 x i32> %res, <64 x i32>* %a
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ret void
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}
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; Vector i64 sdiv are not legal for NEON so use SVE when available.
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define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
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; CHECK-LABEL: sdiv_v1i64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
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; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
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; CHECK: ret
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%res = sdiv <1 x i64> %op1, %op2
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ret <1 x i64> %res
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}
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; Vector i64 sdiv are not legal for NEON so use SVE when available.
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define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
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; CHECK-LABEL: sdiv_v2i64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
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; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
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; CHECK: ret
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%res = sdiv <2 x i64> %op1, %op2
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ret <2 x i64> %res
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}
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define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
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; CHECK-LABEL: sdiv_v4i64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
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; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
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; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <4 x i64>, <4 x i64>* %a
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%op2 = load <4 x i64>, <4 x i64>* %b
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%res = sdiv <4 x i64> %op1, %op2
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store <4 x i64> %res, <4 x i64>* %a
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ret void
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}
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define void @sdiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
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; CHECK-LABEL: sdiv_v8i64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
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; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
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; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <8 x i64>, <8 x i64>* %a
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%op2 = load <8 x i64>, <8 x i64>* %b
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%res = sdiv <8 x i64> %op1, %op2
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store <8 x i64> %res, <8 x i64>* %a
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ret void
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}
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define void @sdiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
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; CHECK-LABEL: sdiv_v16i64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
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; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
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; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <16 x i64>, <16 x i64>* %a
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%op2 = load <16 x i64>, <16 x i64>* %b
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%res = sdiv <16 x i64> %op1, %op2
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store <16 x i64> %res, <16 x i64>* %a
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ret void
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}
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define void @sdiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
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; CHECK-LABEL: sdiv_v32i64:
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; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
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; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
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; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
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; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
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; CHECK: ret
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%op1 = load <32 x i64>, <32 x i64>* %a
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%op2 = load <32 x i64>, <32 x i64>* %b
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%res = sdiv <32 x i64> %op1, %op2
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store <32 x i64> %res, <32 x i64>* %a
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ret void
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}
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;
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; MUL
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;
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