forked from OSchip/llvm-project
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
No functionality change. llvm-svn: 27577
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c10e9a0250
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@ -880,12 +880,21 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1;
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unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1;
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Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
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Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
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SDOperand());
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SDOperand());
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// If we haven't noted the R3/F1 are live out, do so now.
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if (DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(ArgReg);
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break;
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break;
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}
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}
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case 3:
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case 3:
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Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
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Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
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SDOperand());
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SDOperand());
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Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
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Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
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// If we haven't noted the R3+R4 are live out, do so now.
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if (DAG.getMachineFunction().liveout_empty()) {
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DAG.getMachineFunction().addLiveOut(PPC::R3);
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DAG.getMachineFunction().addLiveOut(PPC::R4);
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}
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break;
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break;
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}
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}
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return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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@ -1249,26 +1258,6 @@ PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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}
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}
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}
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}
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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MF.addLiveOut(PPC::R3);
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break;
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case MVT::i64:
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MF.addLiveOut(PPC::R3);
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MF.addLiveOut(PPC::R4);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.addLiveOut(PPC::F1);
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break;
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}
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return ArgValues;
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return ArgValues;
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}
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}
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