forked from OSchip/llvm-project
Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as neverHasSideEffects.
llvm-svn: 169477
This commit is contained in:
parent
16b65394ee
commit
922f10aec4
|
@ -1551,16 +1551,19 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
|
|||
case X86::MOVUPSrm:
|
||||
case X86::MOVAPDrm:
|
||||
case X86::MOVDQArm:
|
||||
case X86::MOVDQUrm:
|
||||
case X86::VMOVSSrm:
|
||||
case X86::VMOVSDrm:
|
||||
case X86::VMOVAPSrm:
|
||||
case X86::VMOVUPSrm:
|
||||
case X86::VMOVAPDrm:
|
||||
case X86::VMOVDQArm:
|
||||
case X86::VMOVDQUrm:
|
||||
case X86::VMOVAPSYrm:
|
||||
case X86::VMOVUPSYrm:
|
||||
case X86::VMOVAPDYrm:
|
||||
case X86::VMOVDQAYrm:
|
||||
case X86::VMOVDQUYrm:
|
||||
case X86::MMX_MOVD64rm:
|
||||
case X86::MMX_MOVQ64rm:
|
||||
case X86::FsVMOVAPSrm:
|
||||
|
|
|
@ -3499,13 +3499,13 @@ def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|||
def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
|
||||
"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
|
||||
VEX, VEX_L;
|
||||
}
|
||||
def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
|
||||
VEX;
|
||||
def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
|
||||
"movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
|
||||
VEX, VEX_L;
|
||||
}
|
||||
|
||||
// For Disassembler
|
||||
let isCodeGenOnly = 1 in {
|
||||
|
@ -3525,7 +3525,8 @@ def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
|
|||
IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
|
||||
}
|
||||
|
||||
let canFoldAsLoad = 1, mayLoad = 1 in {
|
||||
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
|
||||
neverHasSideEffects = 1 in {
|
||||
def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
||||
"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
|
||||
VEX;
|
||||
|
@ -3542,7 +3543,7 @@ let Predicates = [HasAVX] in {
|
|||
}
|
||||
}
|
||||
|
||||
let mayStore = 1 in {
|
||||
let mayStore = 1, neverHasSideEffects = 1 in {
|
||||
def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
|
||||
(ins i128mem:$dst, VR128:$src),
|
||||
"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
|
||||
|
@ -3580,7 +3581,8 @@ def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
|
|||
[], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
|
||||
}
|
||||
|
||||
let canFoldAsLoad = 1, mayLoad = 1 in {
|
||||
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
|
||||
neverHasSideEffects = 1 in {
|
||||
def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
||||
"movdqa\t{$src, $dst|$dst, $src}",
|
||||
[/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
|
||||
|
|
Loading…
Reference in New Issue