From 92252f42c3cc6290d3736466406f5aaa37771da5 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 10 Feb 2004 20:31:28 +0000 Subject: [PATCH] Don't use MachineOperator::is(Phys|Virt)Register llvm-svn: 11276 --- llvm/lib/Target/X86/FloatingPoint.cpp | 2 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/FloatingPoint.cpp b/llvm/lib/Target/X86/FloatingPoint.cpp index 4231776aeefc..0a0fe9b2c2cd 100644 --- a/llvm/lib/Target/X86/FloatingPoint.cpp +++ b/llvm/lib/Target/X86/FloatingPoint.cpp @@ -357,7 +357,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) { } static unsigned getFPReg(const MachineOperand &MO) { - assert(MO.isPhysicalRegister() && "Expected an FP register!"); + assert(MO.isRegister() && "Expected an FP register!"); unsigned Reg = MO.getReg(); assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); return Reg - X86::FP0; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 8911562bfc86..298af02d8aec 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -42,8 +42,8 @@ bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const { // Make sure the instruction is EXACTLY `xchg ax, ax' if (MI.getOpcode() == X86::XCHGrr16) { const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1); - if (op0.isPhysicalRegister() && op0.getReg() == X86::AX && - op1.isPhysicalRegister() && op1.getReg() == X86::AX) { + if (op0.isRegister() && op0.getReg() == X86::AX && + op1.isRegister() && op1.getReg() == X86::AX) { return true; } }