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Don't repeat names and reformat. NFC. 

llvm-svn: 306556
This commit is contained in:
Rafael Espindola 2017-06-28 16:00:16 +00:00
parent 79d21c2a74
commit 920fa14011
1 changed files with 37 additions and 46 deletions
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83
llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
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@ -15,55 +15,47 @@
namespace llvm {
namespace ARM {
enum Fixups {
// fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
// addresses
// 12-bit PC relative relocation for symbol addresses
fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
// fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
// the 16-bit halfwords reordered.
// Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered.
fixup_t2_ldst_pcrel_12,
// fixup_arm_pcrel_10_unscaled - 10-bit PC relative relocation for symbol
// addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
// 10-bit PC relative relocation for symbol addresses used in
// LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
fixup_arm_pcrel_10_unscaled,
// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
// used in VFP instructions where the lower 2 bits are not encoded
// (so it's encoded as an 8-bit immediate).
// 10-bit PC relative relocation for symbol addresses used in VFP instructions
// where the lower 2 bits are not encoded (so it's encoded as an 8-bit
// immediate).
fixup_arm_pcrel_10,
// fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
// the short-swapped encoding of Thumb2 instructions.
// Equivalent to fixup_arm_pcrel_10, accounting for the short-swapped encoding
// of Thumb2 instructions.
fixup_t2_pcrel_10,
// fixup_arm_pcrel_9 - 9-bit PC relative relocation for symbol addresses
// used in VFP instructions where bit 0 not encoded (so it's encoded as an
// 8-bit immediate).
// 9-bit PC relative relocation for symbol addresses used in VFP instructions
// where bit 0 not encoded (so it's encoded as an 8-bit immediate).
fixup_arm_pcrel_9,
// fixup_t2_pcrel_9 - Equivalent to fixup_arm_pcrel_9, accounting for
// the short-swapped encoding of Thumb2 instructions.
// Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding
// of Thumb2 instructions.
fixup_t2_pcrel_9,
// fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
// addresses where the lower 2 bits are not encoded (so it's encoded as an
// 8-bit immediate).
// 10-bit PC relative relocation for symbol addresses where the lower 2 bits
// are not encoded (so it's encoded as an 8-bit immediate).
fixup_thumb_adr_pcrel_10,
// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
// instruction.
// 12-bit PC relative relocation for the ADR instruction.
fixup_arm_adr_pcrel_12,
// fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
// instruction.
// 12-bit PC relative relocation for the ADR instruction.
fixup_t2_adr_pcrel_12,
// fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch
// instructions.
// 24-bit PC relative relocation for conditional branch instructions.
fixup_arm_condbranch,
// fixup_arm_uncondbranch - 24-bit PC relative relocation for
// branch instructions. (unconditional)
// 24-bit PC relative relocation for branch instructions. (unconditional)
fixup_arm_uncondbranch,
// fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
// uconditional branch instructions.
// 20-bit PC relative relocation for Thumb2 direct uconditional branch
// instructions.
fixup_t2_condbranch,
// fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
// branch unconditional branch instructions.
// 20-bit PC relative relocation for Thumb2 direct branch unconditional branch
// instructions.
fixup_t2_uncondbranch,
// fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
// 12-bit fixup for Thumb B instructions.
fixup_arm_thumb_br,
// The following fixups handle the ARM BL instructions. These can be
@ -75,42 +67,41 @@ enum Fixups {
// MachO does not draw a distinction between the two cases, so it will treat
// fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
// fixup_arm_uncondbl - Fixup for unconditional ARM BL instructions.
// Fixup for unconditional ARM BL instructions.
fixup_arm_uncondbl,
// fixup_arm_condbl - Fixup for ARM BL instructions with nontrivial
// conditionalisation.
// Fixup for ARM BL instructions with nontrivial conditionalisation.
fixup_arm_condbl,
// fixup_arm_blx - Fixup for ARM BLX instructions.
// Fixup for ARM BLX instructions.
fixup_arm_blx,
// fixup_arm_thumb_bl - Fixup for Thumb BL instructions.
// Fixup for Thumb BL instructions.
fixup_arm_thumb_bl,
// fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
// Fixup for Thumb BLX instructions.
fixup_arm_thumb_blx,
// fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
// Fixup for Thumb branch instructions.
fixup_arm_thumb_cb,
// fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
// Fixup for Thumb load/store from constant pool instrs.
fixup_arm_thumb_cp,
// fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
// Fixup for Thumb conditional branching instructions.
fixup_arm_thumb_bcc,
// The next two are for the movt/movw pair
// the 16bit imm field are split into imm{15-12} and imm{11-0}
fixup_arm_movt_hi16, // :upper16:
fixup_arm_movw_lo16, // :lower16:
fixup_t2_movt_hi16, // :upper16:
fixup_t2_movw_lo16, // :lower16:
fixup_t2_movt_hi16, // :upper16:
fixup_t2_movw_lo16, // :lower16:
// fixup_arm_mod_imm - Fixup for mod_imm
// Fixup for mod_imm
fixup_arm_mod_imm,
// fixup_t2_so_imm - Fixup for Thumb2 8-bit rotated operand
// Fixup for Thumb2 8-bit rotated operand
fixup_t2_so_imm,
// Marker
@ -118,6 +109,6 @@ enum Fixups {
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
}
}
} // namespace llvm
#endif